[XS] Change in coreboot[main]: soc/intel/xeon_xp: Fix lower ram range bug

[Name of user not set (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85434?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/xeon_xp: Fix lower ram range bug
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soc/intel/xeon_xp: Fix lower ram range bug

Generally the base address of FSP output is already aligned so there is
no need to minus 1. The current code loses 1 byte in the lower DRAM
address space.

Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1
Signed-off-by: Yuchi Chen 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85434/2