Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56915 )
Change subject: mb/google/brya: set PL4 value dynamically for thermal ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/56915/comment/233c0311_5091f71f PS1, Line 29: struct soc_power_limits_config *soc_config; : config_t *conf = config_of_soc(); : soc_config = conf->power_limits_config; nit: this can go down below line 37, and be simplified to: ``` struct soc_power_limits_config *soc_config = config_of_soc()->power_limits_config; soc_config->tdp_pl4... ```
https://review.coreboot.org/c/coreboot/+/56915/comment/ec813f10_a886666e PS1, Line 43: DPTF DPTF does not control PL4, so I would drop that acronym here.