Isaac Christensen (isaac.christensen@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6515
-gerrit
commit 4293a25b1d3ef35c37f5444f559d08457e26c265 Author: David Hendricks dhendrix@chromium.org Date: Wed Aug 28 12:39:11 2013 -0700
armv7: Fix dcache writethrough policy handling
The "bufferable" bit was erroneously set for the writethrough policy making it the same as writeback.
(credit to jwerner for pointing this out) Signed-off-by: David Hendricks dhendrix@chromium.org
Change-Id: I567d57f0e522cb4b82988894ba9b4638642bf8db Reviewed-on: https://chromium-review.googlesource.com/167323 Reviewed-by: Julius Werner jwerner@chromium.org Tested-by: David Hendricks dhendrix@chromium.org Tested-by: ron minnich rminnich@chromium.org Commit-Queue: David Hendricks dhendrix@chromium.org (cherry picked from commit 36cf13839604c349692865475f3011afd08965b4) Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com --- src/arch/armv7/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/armv7/mmu.c b/src/arch/armv7/mmu.c index 7d6d46a..a350895 100644 --- a/src/arch/armv7/mmu.c +++ b/src/arch/armv7/mmu.c @@ -92,7 +92,7 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, str = "writeback"; break; case DCACHE_WRITETHROUGH: - attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2; + attr = (0x3 << 10) | (1 << 3) | 0x2; str = "writethrough"; break; default: