Change in coreboot[master]: soc/skylake: Enable LAN depending on devicetree configuration
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLAN, but this is duplicate to the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLAN setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 20 files changed, 3 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 9d7d35f..4d6707e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -36,7 +36,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 541dc4f..24b88a5 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -134,8 +134,6 @@ .voltage_limit = 1520 \ }"
- register "EnableLan" = "0" - # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 4fb2c69..6c2b75a 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -47,7 +47,6 @@ register "Cio2Enable" = "0" register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" - register "EnableLan" = "1"
register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index ad93bb7..c244199 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -36,7 +36,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 966b0bb..1907f83 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,7 +65,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index cda2adf..39402a0 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -38,7 +38,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 31d7bc0..a3935c9 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -42,7 +42,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 73aef8a..6b31960 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index ce2b35a..89e953c 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "EnableAzalia" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index acac9e9..3b696ed 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,7 +37,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 64c5bd8..c9506b5 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -42,7 +42,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8499446..28af6d6 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b5979fc..a8e5195 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -50,8 +50,6 @@ # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7"
- register EnableLan = "1" - # USB related register "SsicPortEnable" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index b296926..6e16606 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,8 +140,6 @@ register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1"
- register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 353e03a..c414e02 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -38,7 +38,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index b460f74..8bc85e7 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,7 +34,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "EnableAzalia" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 1751f63..67ea0c4 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -45,7 +45,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 711e04c..1d6e77e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -27,7 +27,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8a95d5e..5d5296f 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -242,8 +242,9 @@ params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
- params->PchLanEnable = config->EnableLan; - if (config->EnableLan) { + dev = pcidev_path_on_root(PCH_DEVFN_GBE); + params->PchLanEnable = dev ? dev->enabled : 0; + if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; params->PchLanClkReqSupported = config->LanClkReqSupported; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index cd372be..a3d5d46 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -149,7 +149,6 @@ u8 CmdTriStateDis;
/* Lan */ - u8 EnableLan; u8 EnableLanLtr; u8 EnableLanK1Off; u8 LanClkReqSupported;
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43844
to look at the new patch set (#2).
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLAN, but this is duplicate to the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLAN setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43844/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43844/2//COMMIT_MSG@9 PS2, Line 9: this is : duplicate to the devicetree on/off options.
… this duplicates the devicetree on/off options.
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Paul Menzel, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43844
to look at the new patch set (#3).
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLAN, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLAN setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/3
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Paul Menzel, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43844
to look at the new patch set (#4).
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLAN, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLAN setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/4
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Paul Menzel, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43844
to look at the new patch set (#5).
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLAN, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLAN setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/5
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43844/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43844/2//COMMIT_MSG@9 PS2, Line 9: this is : duplicate to the devicetree on/off options.
… this duplicates the devicetree on/off options.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
Patch Set 5: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/43844/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43844/5//COMMIT_MSG@9 PS5, Line 9: EnableLAN EnableLan
https://review.coreboot.org/c/coreboot/+/43844/5//COMMIT_MSG@14 PS5, Line 14: EnableLAN EnableLan
https://review.coreboot.org/c/coreboot/+/43844/5/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43844/5/src/soc/intel/skylake/chip.... PS5, Line 246: dev ? dev->enabled : 0 `dev && dev->enabled`
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Paul Menzel, Angel Pons, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43844
to look at the new patch set (#6).
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/6
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/skylake: Enable LAN depending on devicetree configuration ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/43844/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43844/5//COMMIT_MSG@9 PS5, Line 9: EnableLAN
EnableLan
Done
https://review.coreboot.org/c/coreboot/+/43844/5//COMMIT_MSG@14 PS5, Line 14: EnableLAN
EnableLan
Done
https://review.coreboot.org/c/coreboot/+/43844/5/src/soc/intel/skylake/chip.... File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/43844/5/src/soc/intel/skylake/chip.... PS5, Line 246: dev ? dev->enabled : 0
`dev && dev->enabled`
I would leave it like that to keep the consistency, since the existing code is handled like that.
Hello build bot (Jenkins), Michał Żygowski, Frans Hendriks, Paul Menzel, Angel Pons, Patrick Rudolph, Wim Vervoorn, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43844
to look at the new patch set (#7).
Change subject: soc/intel/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43844/7
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/intel/skylake: Enable LAN depending on devicetree configuration ......................................................................
Patch Set 8: Code-Review+2
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/intel/skylake: Enable LAN depending on devicetree configuration ......................................................................
Removed Code-Review+2 by Angel Pons th3fanbus@gmail.com
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43844 )
Change subject: soc/intel/skylake: Enable LAN depending on devicetree configuration ......................................................................
soc/intel/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 21 files changed, 3 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 398271e..69469b911 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -36,7 +36,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index c185b10..9b56f42 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -125,8 +125,6 @@ .voltage_limit = 1520 \ }"
- register "EnableLan" = "0" - # USB register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index f9a2b66..4b08819 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -47,7 +47,6 @@ register "Cio2Enable" = "0" register "PmTimerDisabled" = "1" register "HeciEnabled" = "0" - register "EnableLan" = "1"
register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 64241f8..767c77b 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -36,7 +36,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 4bd4d33..250b96d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,7 +65,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 739ecc6..bbfa79f 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -38,7 +38,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 2634a57..7c4928d 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -42,7 +42,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 67864f4..7bbddbd 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 1bb88ab..e9514e0 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "EnableAzalia" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 7b0fe60..e9d7dea 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 3d255c1..a5c905e 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,7 +37,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index e669fe5..32429f9c 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -42,7 +42,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ec896eb..2970a2e 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -32,7 +32,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b5979fc..a8e5195 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -50,8 +50,6 @@ # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7"
- register EnableLan = "1" - # USB related register "SsicPortEnable" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7110279..5a24705 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,8 +140,6 @@ register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1"
- register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index b1ffb56..67b56ff 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -38,7 +38,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 40f0d19..ef2cfbb 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,7 +34,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "EnableAzalia" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6e24f5a..6943505 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -45,7 +45,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 9a1ca31..8a369b7 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -27,7 +27,6 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 3a9dd5c..3267d86e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -242,8 +242,9 @@ params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
- params->PchLanEnable = config->EnableLan; - if (config->EnableLan) { + dev = pcidev_path_on_root(PCH_DEVFN_GBE); + params->PchLanEnable = dev ? dev->enabled : 0; + if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; params->PchLanClkReqSupported = config->LanClkReqSupported; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a9c69cf..b243bde 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -136,7 +136,6 @@ u8 CmdTriStateDis;
/* Lan */ - u8 EnableLan; u8 EnableLanLtr; u8 EnableLanK1Off; u8 LanClkReqSupported;
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Michael Niewöhner (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)