Change in coreboot[master]: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode

[Raul Rangel (Code Review)]

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61522 )

Change subject: soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
......................................................................

soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode

This will allow verstage to write post codes.

BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214   03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new

Signed-off-by: Raul E Rangel 
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522
Reviewed-by: Kangheui Won 
Reviewed-by: Karthik Ramasubramanian 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/cezanne/psp_verstage/chipset.c
M src/soc/amd/cezanne/psp_verstage/svc.c
M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
3 files changed, 8 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Kangheui Won: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/psp_verstage/chipset.c b/src/soc/amd/cezanne/psp_verstage/chipset.c
index 30f613a..41d318e 100644
--- a/src/soc/amd/cezanne/psp_verstage/chipset.c
+++ b/src/soc/amd/cezanne/psp_verstage/chipset.c
@@ -40,13 +40,3 @@
    else
    	svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_PRODUCTION);
 }
-
-
-/* Functions below are stub functions for not-yet-implemented PSP features.
- * These functions should be replaced with proper implementations later.
- */
-
-uint32_t svc_write_postcode(uint32_t postcode)
-{
-	return 0;
-}
diff --git a/src/soc/amd/cezanne/psp_verstage/svc.c b/src/soc/amd/cezanne/psp_verstage/svc.c
index 78f7126..12fccc3 100644
--- a/src/soc/amd/cezanne/psp_verstage/svc.c
+++ b/src/soc/amd/cezanne/psp_verstage/svc.c
@@ -140,3 +140,10 @@
    SVC_CALL1(SVC_SET_PLATFORM_BOOT_MODE, (uint32_t)boot_mode, retval);
    return retval;
 }
+
+uint32_t svc_write_postcode(uint32_t postcode)
+{
+	uint32_t retval = 0;
+	SVC_CALL1(SVC_WRITE_POSTCODE, postcode, retval);
+	return retval;
+}
diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
index ff2144d..4cf9e70 100644
--- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
+++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
@@ -51,6 +51,7 @@
 #define SVC_SHA                             0x69
 #define SVC_CCP_DMA                         0x6A
 #define SVC_SET_PLATFORM_BOOT_MODE          0x6C
+#define SVC_WRITE_POSTCODE                  0x6D

struct mod_exp_params {
    char		*pExponent;	// Exponent address