Change in coreboot[master]: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree ......................................................................
mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork
Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c 2 files changed, 9 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/44890/1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 62395a1..46ca699 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -180,6 +180,15 @@
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+ # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index 49d8ade..7ce78d9 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -31,7 +31,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ4, }, { // WLAN @@ -45,7 +44,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, }, { // SD Reader @@ -59,7 +57,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, } };
@@ -76,7 +73,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ4, }, { // WLAN @@ -90,7 +86,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, }, { // SD Reader @@ -104,7 +99,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, } };
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 1:
please test before merging
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG@8 PS1, Line 8: You should probably describe why you're pulling those values from the descriptors. Similarly, are we certain AGESA isn't doing something it shouldn't prior to the native coreboot code kicking in? And how that lines up w/ the pcie configuration?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 1: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG@8 PS1, Line 8:
You should probably describe why you're pulling those values from the descriptors. […]
seems like those shouldn't be dropped from the descriptor, since that will affect other registers as well. I'll have a closer look
Hello build bot (Jenkins), Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44890
to look at the new patch set (#2).
Change subject: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree ......................................................................
mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork
Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/44890/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44890/1//COMMIT_MSG@8 PS1, Line 8:
seems like those shouldn't be dropped from the descriptor, since that will affect other registers as […]
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree ......................................................................
mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork
Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 4413857..1620643 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -180,6 +180,15 @@
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+ # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44890 )
Change subject: mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 6/1/7 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17321 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17320 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/17319 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17318 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/17317 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17323 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17322
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aaron Durbin (Code Review)
-
Felix Held (Code Review)
-
Patrick Georgi (Code Review)