Change in coreboot[master]: mb/google/zork: Configure GPIO_40 as drive low in sleep path

[Furquan Shaikh (Code Review)]

Hello Aaron Durbin,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42935

to review the following change.

Change subject: mb/google/zork: Configure GPIO_40 as drive low in sleep path
......................................................................

mb/google/zork: Configure GPIO_40 as drive low in sleep path

This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in
sleep path so that the PERST# to NVMe device keeps asserted until
coreboot reconfigures it as high on S3 resume path. This is similar to
the earlier change for PCIE_RST1_L but helps platforms that use
NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain,
hence it retains state across S3 entry/exit.

Signed-off-by: Furquan Shaikh 
Change-Id: Ie79e946eee8f393863630226ae2183e653030415
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+...
Reviewed-by: Aaron Durbin 
Commit-Queue: Furquan Shaikh 
Tested-by: Furquan Shaikh 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42935/1

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index 1dd2dd5..aacf14b 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -36,6 +36,8 @@
    PAD_GPO(GPIO_5, LOW),
    /* PCIE_RST1_L */
    PAD_GPO(GPIO_27, LOW),
+	/* NVME_AUX_RESET_L */
+	PAD_GPO(GPIO_40, LOW),
    /* EN_PWR_CAMERA */
    PAD_GPO(GPIO_76, LOW),
 };

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42935 )

Change subject: mb/google/zork: Configure GPIO_40 as drive low in sleep path
......................................................................

Patch Set 1: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42935 )

Change subject: mb/google/zork: Configure GPIO_40 as drive low in sleep path
......................................................................

mb/google/zork: Configure GPIO_40 as drive low in sleep path

This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in
sleep path so that the PERST# to NVMe device keeps asserted until
coreboot reconfigures it as high on S3 resume path. This is similar to
the earlier change for PCIE_RST1_L but helps platforms that use
NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain,
hence it retains state across S3 entry/exit.

Signed-off-by: Furquan Shaikh 
Change-Id: Ie79e946eee8f393863630226ae2183e653030415
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+...
Reviewed-by: Aaron Durbin 
Commit-Queue: Furquan Shaikh 
Tested-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42935
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index 1dd2dd5..aacf14b 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -36,6 +36,8 @@
    PAD_GPO(GPIO_5, LOW),
    /* PCIE_RST1_L */
    PAD_GPO(GPIO_27, LOW),
+	/* NVME_AUX_RESET_L */
+	PAD_GPO(GPIO_40, LOW),
    /* EN_PWR_CAMERA */
    PAD_GPO(GPIO_76, LOW),
 };