Change in coreboot[master]: soc/intel/common: Include Meteor Lake device IDs

[Wonkyu Kim (Code Review)]

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62581 )

Change subject: soc/intel/common: Include Meteor Lake device IDs
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Patch Set 6:

(1 comment)

File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/62581/comment/eadce721_98835c85 
PS1, Line 3431: #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP9		0x7e4d
              : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP10		0x7eca
              : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP11		0x7ecb
              : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP12		0x7ecc
> > There is no CPU RPs in MTL. […]

We can do that but only concern is that it's not inline with FSP UPD setting.

* need to use bit 9-11 for RP10-12
PcieRpEnableMask

* need to use 9 - 11 for RP10-12
PcieClkSrcUsage, PcieClkSrcClkReq, PcieRpL1Substates, PcieRpLtrEnable, PcieRpAdvancedErrorReporting, PcieRpHotPlug, PcieRpClkReqDetect