Change in coreboot[master]: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition
Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition ......................................................................
mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, as the EC_SYNC_IRQ line.
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- enable itss for inverting the EC_SYNC_IRQ gpio for the APIC
- add EC_SYNC_IRQ to the group of chromeos_gpios for use by depthcharge
- change incorrect EC_SYNC_IRQ define from GPP_D17_IRQ to GPP_D17
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 4 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35174/1
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index fda8c9e..8952a5f 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -194,6 +194,7 @@ select NO_FADT_8042 select VARIANT_HAS_CAMERA_ACPI select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
config VARIANT_SPECIFIC_OPTIONS_RAMMUS def_bool n diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 84b0031..b72e40c 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -32,6 +32,9 @@ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, +#if CONFIG_BOARD_GOOGLE_NOCTURNE + {EC_SYNC_IRQ, ACTIVE_LOW, gpio_get(EC_SYNC_IRQ), "EC sync irq"}, +#endif }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index c62317a..a4ea3c3 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -196,7 +196,7 @@ /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ PAD_CFG_NC(GPP_D18), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h index fb7ad1a..105e158 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h @@ -34,8 +34,8 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK
-/* EC sync irq is GPP_D12 */ -#define EC_SYNC_IRQ GPP_D17_IRQ +/* EC sync irq is GPP_D17 */ +#define EC_SYNC_IRQ GPP_D17
/* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35174
to look at the new patch set (#2).
Change subject: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition ......................................................................
mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, as the EC_SYNC_IRQ line.
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- enable itss for inverting the EC_SYNC_IRQ gpio for the APIC
- add EC_SYNC_IRQ to the group of chromeos_gpios for use by depthcharge
- change incorrect EC_SYNC_IRQ define from GPP_D17_IRQ to GPP_D17
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 4 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35174/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/Kconfig:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 197: select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG If this is required this should be done at the SoC level. There is nothing mainboard-specific about this.
Actually, I see that it is already set here: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/pch/.... Does that not take effect for KBL?
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 36: EC_SYNC_IRQ Do you intend to pass the IRQ#, GPIO# or GPE# here?
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 38: GPP_D17_IRQ Changing this would break the OS level interrupt resource: https://review.coreboot.org/cgit/coreboot.git/tree/src/ec/google/chromeec/ac...
Hello Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35174
to look at the new patch set (#3).
Change subject: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition ......................................................................
mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, as the EC_SYNC_IRQ line.
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- enable itss for inverting the EC_SYNC_IRQ gpio for the APIC
- add EC_SYNC_IRQ to the group of chromeos_gpios for use by depthcharge
- change incorrect EC_SYNC_IRQ define from GPP_D17_IRQ to GPP_D17
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 3 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35174/3
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: fix EC_SYNC_IRQ definition ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/Kconfig:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 197: select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
If this is required this should be done at the SoC level. […]
Done
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 36: EC_SYNC_IRQ
Do you intend to pass the IRQ#, GPIO# or GPE# here?
GPIO#
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 38: GPP_D17_IRQ
Changing this would break the OS level interrupt resource: https://review.coreboot. […]
EC_ENABLE_SYNC_IRQ is not set for nocturne. Should it be? I couldn't find where in the kernel the information exported in the _CRS gets accessed to determine exactly what it is used for. There is also a newer EC_ENABLE_SYNC_GPIO in the top-of-tree branch (but not nocturne branch), but aside from it exporting the EC_SYNC_IRQ using a different header type (EC_ENABLE_SYNC_GPIO defines a "GpioInt" whereas EC_ENABLE_SYNC_IRQ defines an "Interrupt"), I couldn't tell how exactly it was being used by the kernel.
Hello Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35174
to look at the new patch set (#4).
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 3 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35174/4
Hello Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35174
to look at the new patch set (#5).
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO.
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 3 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35174/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 38: GPP_D17_IRQ
EC_ENABLE_SYNC_IRQ is not set for nocturne. Should it be?
It is done here: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/popp...
Kernel uses it here: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads... https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads...
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... PS5, Line 35: CONFIG(BOARD_GOOGLE_NOCTURNE) #ifdef EC_SYNC_GPIO?
That way it can be used by more variants of poppy that have this EC_SYNC_GPIO.
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/gpio.c:
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... PS5, Line 199: PAD_CFG_GPI_APIC_INVERT Just curious: If you are just passing the GPIO# to depthcharge from coreboot, does this INVERT really make any difference?
Hello Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35174
to look at the new patch set (#6).
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 3 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35174/6
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... PS5, Line 35: CONFIG(BOARD_GOOGLE_NOCTURNE)
#ifdef EC_SYNC_GPIO? […]
Good idea.
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/gpio.c:
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... PS5, Line 199: PAD_CFG_GPI_APIC_INVERT
Just curious: If you are just passing the GPIO# to depthcharge from coreboot, does this INVERT reall […]
It does not make a difference for the functionality in depthcharge. Volume buttons work in depthcharge either way.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 36: EC_SYNC_IRQ
GPIO#
Done
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/chromeos.c:
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... PS5, Line 35: CONFIG(BOARD_GOOGLE_NOCTURNE)
Good idea.
Done
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/gpio.c:
https://review.coreboot.org/c/coreboot/+/35174/5/src/mainboard/google/poppy/... PS5, Line 199: PAD_CFG_GPI_APIC_INVERT
It does not make a difference for the functionality in depthcharge. […]
Done
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... File src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/35174/2/src/mainboard/google/poppy/... PS2, Line 38: GPP_D17_IRQ
EC_ENABLE_SYNC_IRQ is not set for nocturne. Should it be? […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35174 )
Change subject: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO ......................................................................
mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/poppy/variants/nocturne/gpio.c M src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h 3 files changed, 8 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 84b0031..23e575d 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -32,6 +32,9 @@ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, +#ifdef EC_SYNC_GPIO + {EC_SYNC_GPIO, ACTIVE_LOW, gpio_get(EC_SYNC_GPIO), "EC sync gpio"}, +#endif }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index c62317a..a4ea3c3 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -196,7 +196,7 @@ /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ PAD_CFG_NC(GPP_D18), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h index fb7ad1a..45bb76b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h @@ -34,9 +34,12 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK
-/* EC sync irq is GPP_D12 */ +/* EC sync irq is tied to GPP_D17 */ #define EC_SYNC_IRQ GPP_D17_IRQ
+/* EC sync gpio */ +#define EC_SYNC_GPIO GPP_D17 + /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI
-
Furquan Shaikh (Code Review) -
Nick Vaccaro (Code Review)
-
Patrick Georgi (Code Review)