Change in coreboot[master]: Revert "mb/google/brya: Enable south XHCI ports 1 and 2"

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Ronak Kanabar, Subrata Banik, EricR Lai.
Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, EricR Lai,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/56132

to review the following change.

Change subject: Revert "mb/google/brya: Enable south XHCI ports 1 and 2"
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Revert "mb/google/brya: Enable south XHCI ports 1 and 2"

This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f.

Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable

Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
1 file changed, 0 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56132/1

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index d7e2522..3155d04 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -39,12 +39,6 @@
    register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
-	# TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081
-	# uses port enable for south XHCI ports to determine if TCSS
-	# ports should be enabled. Until FSP is fixed, enable south
-	# XHCI ports 1 and 2.
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
    register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

register "SerialIoI2cMode" = "{