Change in coreboot[master]: soc/intel/broadwell: Align memmap.h with Haswell - coreboot-gerrit

29 Oct 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46956 )
Change subject: soc/intel/broadwell: Align memmap.h with Haswell
......................................................................
soc/intel/broadwell: Align memmap.h with Haswell
This is merely to reduce cosmetic differences.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I473336a77179a3d1d26933f481abded49e9f0864
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/acpi/ctdp.asl
M src/soc/intel/broadwell/acpi/hostbridge.asl
M src/soc/intel/broadwell/early_init.c
M src/soc/intel/broadwell/haswell.h
M src/soc/intel/broadwell/memmap.h
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/acpi/gpio.asl
M src/soc/intel/broadwell/pch/acpi/lpc.asl
M src/soc/intel/broadwell/pch/acpi/pch.asl
M src/soc/intel/broadwell/pch/bootblock.c
M src/soc/intel/broadwell/pch/fadt.c
M src/soc/intel/broadwell/pch/gpio.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/pm.h
M src/soc/intel/broadwell/pch/pmutil.c
M src/soc/intel/broadwell/pch/power_state.c
M src/soc/intel/broadwell/pch/rcba.h
M src/soc/intel/broadwell/pch/smbus.c
M src/soc/intel/broadwell/pch/smi.c
M src/soc/intel/broadwell/pei_data.c
21 files changed, 82 insertions(+), 97 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46956/1

diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index fc41259..db9aced 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -27,7 +27,7 @@
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
    current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-					     MCFG_BASE_ADDRESS, 0, 0, 255);
+					     CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255);
    return current;
 }
diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl
index b18ec78..d4f6a1b 100644
--- a/src/soc/intel/broadwell/acpi/ctdp.asl
+++ b/src/soc/intel/broadwell/acpi/ctdp.asl
@@ -9,7 +9,7 @@
    Name (CTCU, 2)		/* CTDP Up Select */
    Name (SPL1, 0)		/* Saved PL1 value */
-	OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000)
+	OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000)
    Field (MCHB, DWordAcc, Lock, Preserve)
    {
    	Offset (0x930), /* PACKAGE_POWER_SKU */
diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl
index 607178c..8b63ec7 100644
--- a/src/soc/intel/broadwell/acpi/hostbridge.asl
+++ b/src/soc/intel/broadwell/acpi/hostbridge.asl
@@ -174,11 +174,11 @@
    Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
-		Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
-		Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
-		Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
-		Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
-		Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+		Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x4000)
+		Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x8000)
+		Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x1000)
+		Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x1000)
+		Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
    	Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
    	Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
    })
diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c
index af5ba14..31786f3 100644
--- a/src/soc/intel/broadwell/early_init.c
+++ b/src/soc/intel/broadwell/early_init.c
@@ -11,9 +11,9 @@
 static void broadwell_setup_bars(void)
 {
    /* Set up all hardcoded northbridge BARs */
-	pci_write_config32(HOST_BRIDGE, MCHBAR, MCH_BASE_ADDRESS | 1);
-	pci_write_config32(HOST_BRIDGE, DMIBAR, DMI_BASE_ADDRESS | 1);
-	pci_write_config32(HOST_BRIDGE, EPBAR,  EP_BASE_ADDRESS  | 1);
+	pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1);
+	pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1);
+	pci_write_config32(HOST_BRIDGE, EPBAR,  DEFAULT_EPBAR  | 1);
MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1;
    MCHBAR32(GDXCBAR)  =  GDXC_BASE_ADDRESS | 1;
diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h
index dfce0fd..df3a7550 100644
--- a/src/soc/intel/broadwell/haswell.h
+++ b/src/soc/intel/broadwell/haswell.h
@@ -85,9 +85,9 @@
/* MCHBAR */
-#define MCHBAR8(x)	*((volatile u8  *)(MCH_BASE_ADDRESS + (x)))
-#define MCHBAR16(x)	*((volatile u16 *)(MCH_BASE_ADDRESS + (x)))
-#define MCHBAR32(x)	*((volatile u32 *)(MCH_BASE_ADDRESS + (x)))
+#define MCHBAR8(x)	*((volatile u8  *)(DEFAULT_MCHBAR + (x)))
+#define MCHBAR16(x)	*((volatile u16 *)(DEFAULT_MCHBAR + (x)))
+#define MCHBAR32(x)	*((volatile u32 *)(DEFAULT_MCHBAR + (x)))
/* Memory controller characteristics */
 #define NUM_CHANNELS	2
diff --git a/src/soc/intel/broadwell/memmap.h b/src/soc/intel/broadwell/memmap.h
index 241569e..e69b88e 100644
--- a/src/soc/intel/broadwell/memmap.h
+++ b/src/soc/intel/broadwell/memmap.h
@@ -3,17 +3,9 @@
 #ifndef _BROADWELL_IOMAP_H_
 #define _BROADWELL_IOMAP_H_
-#define MCFG_BASE_ADDRESS	CONFIG_MMCONF_BASE_ADDRESS
-#define MCFG_BASE_SIZE		0x4000000
-
-#define MCH_BASE_ADDRESS	0xfed10000
-#define MCH_BASE_SIZE		0x8000
-
-#define DMI_BASE_ADDRESS	0xfed18000
-#define DMI_BASE_SIZE		0x1000
-
-#define EP_BASE_ADDRESS		0xfed19000
-#define EP_BASE_SIZE		0x1000
+#define DEFAULT_MCHBAR		0xfed10000
+#define DEFAULT_DMIBAR		0xfed18000
+#define DEFAULT_EPBAR		0xfed19000
#define EDRAM_BASE_ADDRESS	0xfed80000
 #define EDRAM_BASE_SIZE		0x4000
@@ -21,10 +13,7 @@
 #define GDXC_BASE_ADDRESS	0xfed84000
 #define GDXC_BASE_SIZE		0x1000
-#define RCBA_BASE_ADDRESS	0xfed1c000
-#define RCBA_BASE_SIZE		0x4000
-
-#define HPET_BASE_ADDRESS	0xfed00000
+#define DEFAULT_RCBA		0xfed1c000
#define GFXVT_BASE_ADDRESS	0xfed90000ULL
 #define GFXVT_BASE_SIZE		0x1000
@@ -32,14 +21,10 @@
 #define VTVC0_BASE_ADDRESS	0xfed91000ULL
 #define VTVC0_BASE_SIZE		0x1000
-#define ACPI_BASE_ADDRESS	0x1000
-#define ACPI_BASE_SIZE		0x100
+#define DEFAULT_PMBASE		0x1000
-#define GPIO_BASE_ADDRESS	0x1400
-#define GPIO_BASE_SIZE		0x400
-
-#define SMBUS_BASE_ADDRESS	0x0400
-#define SMBUS_BASE_SIZE		0x10
+#define DEFAULT_GPIOBASE	0x1400
+#define DEFAULT_GPIOSIZE	0x400
/* Temporary addresses used in romstage */
 #define EARLY_GTT_BAR		0xe0000000
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index 33293a4..1319a02 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -115,9 +115,9 @@
struct fixed_mmio_descriptor mc_fixed_resources[] = {
    { PCIEXBAR, 0,               get_pcie_bar,      "PCIEXBAR" },
-	{ MCHBAR,   MCH_BASE_SIZE,   get_bar,           "MCHBAR"   },
-	{ DMIBAR,   DMI_BASE_SIZE,   get_bar,           "DMIBAR"   },
-	{ EPBAR,    EP_BASE_SIZE,    get_bar,           "EPBAR"    },
+	{ MCHBAR,   0x8000,   get_bar,           "MCHBAR"   },
+	{ DMIBAR,   0x1000,   get_bar,           "DMIBAR"   },
+	{ EPBAR,    0x1000,    get_bar,           "EPBAR"    },
    { GDXCBAR,  GDXC_BASE_SIZE,  get_bar_in_mchbar, "GDXCBAR"  },
    { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" },
 };
diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl
index 6b20f27..afbd4d6 100644
--- a/src/soc/intel/broadwell/pch/acpi/gpio.asl
+++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl
@@ -41,9 +41,9 @@
    	CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
    	CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
-		BLEN = GPIO_BASE_SIZE
-		BMIN = GPIO_BASE_ADDRESS
-		BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1
+		BLEN = DEFAULT_GPIOSIZE
+		BMIN = DEFAULT_GPIOBASE
+		BMAX = DEFAULT_GPIOBASE + DEFAULT_GPIOSIZE - 1
Return (RBUF)
    }
diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl
index ae54ce3..5f69d7c 100644
--- a/src/soc/intel/broadwell/pch/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl
@@ -155,7 +155,7 @@
    		IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
    		IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
    		IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff)
+			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff)
    	})
Method (_CRS, 0, NotSerialized)
diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl
index c7c6207..b10c62d 100644
--- a/src/soc/intel/broadwell/pch/acpi/pch.asl
+++ b/src/soc/intel/broadwell/pch/acpi/pch.asl
@@ -15,7 +15,7 @@
    }
// Root Complex Register Block
-	OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+	OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
    Field (RCRB, DWordAcc, Lock, Preserve)
    {
    	Offset (0x3404), // High Performance Timer Configuration
diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c
index 79cfe90..fa6ff95 100644
--- a/src/soc/intel/broadwell/pch/bootblock.c
+++ b/src/soc/intel/broadwell/pch/bootblock.c
@@ -14,7 +14,7 @@
static void map_rcba(void)
 {
-	pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1);
+	pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1);
 }
static void enable_port80_on_lpc(void)
@@ -49,13 +49,13 @@
 static void pch_enable_bars(void)
 {
    /* Set up southbridge BARs */
-	pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1);
+	pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1);
-	pci_write_config32(PCH_LPC_DEV, PMBASE, ACPI_BASE_ADDRESS | 1);
+	pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIO functionality. */
    pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, GPIO_EN);
@@ -89,15 +89,15 @@
    (void)RCBA32(HPTC);
/* Enable HPET to start counter */
-	setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0);
+	setbits32((void *)CONFIG_HPET_ADDRESS + 0x10, 1 << 0);
/* Disable reset */
    RCBA32_OR(GCS, 1 << 5);
/* TCO timer halt */
-	u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT);
+	u16 reg16 = inb(DEFAULT_PMBASE + TCO1_CNT);
    reg16 |= TCO_TMR_HLT;
-	outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT);
+	outb(reg16, DEFAULT_PMBASE + TCO1_CNT);
/* Enable upper 128 bytes of CMOS */
    RCBA32_OR(RC, 1 << 2);
diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c
index 5679541..39e3508 100644
--- a/src/soc/intel/broadwell/pch/fadt.c
+++ b/src/soc/intel/broadwell/pch/fadt.c
@@ -8,7 +8,7 @@
void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
-	const uint16_t pmbase = ACPI_BASE_ADDRESS;
+	const uint16_t pmbase = DEFAULT_PMBASE;
fadt->sci_int = 9;
diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/soc/intel/broadwell/pch/gpio.c
index eac484c..d61670d 100644
--- a/src/soc/intel/broadwell/pch/gpio.c
+++ b/src/soc/intel/broadwell/pch/gpio.c
@@ -53,8 +53,8 @@
    		break;
/* Setup Configuration registers 1 and 2 */
-		outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio));
-		outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio));
+		outl(entry->conf0, DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio));
+		outl(entry->conf1, DEFAULT_GPIOBASE + GPIO_CONFIG1(gpio));
/* Determine set and bit based on GPIO number */
    	set = gpio >> 5;
@@ -78,14 +78,14 @@
    }
for (set = 0; set <= 2; set++) {
-		outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set));
-		outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set));
-		outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set));
-		outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set));
+		outl(owner[set], DEFAULT_GPIOBASE + GPIO_OWNER(set));
+		outl(route[set], DEFAULT_GPIOBASE + GPIO_ROUTE(set));
+		outl(irqen[set], DEFAULT_GPIOBASE + GPIO_IRQ_IE(set));
+		outl(reset[set], DEFAULT_GPIOBASE + GPIO_RESET(set));
    }
-	outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK);
-	outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN);
+	outl(blink, DEFAULT_GPIOBASE + GPIO_BLINK);
+	outl(pirq2apic, DEFAULT_GPIOBASE + GPIO_PIRQ_APIC_EN);
 }
int get_gpio(int gpio_num)
@@ -93,7 +93,7 @@
    if (gpio_num > MAX_GPIO_NUMBER)
    	return 0;
-	return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
+	return !!(inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
 }
/*
@@ -122,13 +122,13 @@
    if (gpio_num > MAX_GPIO_NUMBER)
    	return;
-	conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
+	conf0 = inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num));
    conf0 &= ~GPO_LEVEL_MASK;
    conf0 |= value << GPO_LEVEL_SHIFT;
-	outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num));
+	outl(conf0, DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num));
 }
int gpio_is_native(int gpio_num)
 {
-	return !(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & 1);
+	return !(inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)) & 1);
 }
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 2114a84..d5ecdeb 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -194,10 +194,10 @@
    pci_write_config16(dev, GEN_PMCON_3, reg16);
/* Prepare sleep mode */
-	reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	reg32 = inl(DEFAULT_PMBASE + PM1_CNT);
    reg32 &= ~SLP_TYP;
    reg32 |= SCI_EN;
-	outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT);
+	outl(reg32, DEFAULT_PMBASE + PM1_CNT);
/* Set up NMI on errors */
    reg8 = inb(0x61);
@@ -499,9 +499,9 @@
    res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* RCBA */
-	if (default_decode_base > RCBA_BASE_ADDRESS) {
+	if (default_decode_base > DEFAULT_RCBA) {
    	res = new_resource(dev, RCBA);
-		res->base = RCBA_BASE_ADDRESS;
+		res->base = DEFAULT_RCBA;
    	res->size = 16 * 1024;
    	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
    		     IORESOURCE_FIXED | IORESOURCE_RESERVE;
@@ -583,11 +583,11 @@
    res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIOBASE */
-	pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS,
-				GPIO_BASE_SIZE, GPIO_BASE);
+	pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE,
+				DEFAULT_GPIOSIZE, GPIO_BASE);
/* PMBASE */
-	pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
+	pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 0x100, PMBASE);
/* LPC Generic IO Decode range. */
    if (dev->chip_info) {
diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/soc/intel/broadwell/pch/pm.h
index 40467ed..7e9e1a5 100644
--- a/src/soc/intel/broadwell/pch/pm.h
+++ b/src/soc/intel/broadwell/pch/pm.h
@@ -5,7 +5,7 @@
#include <acpi/acpi.h>
-/* ACPI_BASE_ADDRESS / PMBASE */
+/* DEFAULT_PMBASE / PMBASE */
#define PM1_STS			0x00
 #define  WAK_STS		(1 << 15)
diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c
index cc61715..e8af6cc 100644
--- a/src/soc/intel/broadwell/pch/pmutil.c
+++ b/src/soc/intel/broadwell/pch/pmutil.c
@@ -24,7 +24,7 @@
static inline uint16_t get_gpiobase(void)
 {
-	return GPIO_BASE_ADDRESS;
+	return DEFAULT_GPIOBASE;
 }
/* Print status bits with descriptive names */
@@ -424,5 +424,5 @@
 /* STM Support */
 uint16_t get_pmbase(void)
 {
-	return (uint16_t) ACPI_BASE_ADDRESS;
+	return (uint16_t) DEFAULT_PMBASE;
 }
diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c
index bb80550..562b876 100644
--- a/src/soc/intel/broadwell/pch/power_state.c
+++ b/src/soc/intel/broadwell/pch/power_state.c
@@ -50,7 +50,7 @@
    		break;
    	}
    	/* Clear SLP_TYP. */
-		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+		outl(ps->pm1_cnt & ~(SLP_TYP), DEFAULT_PMBASE + PM1_CNT);
    }
if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
@@ -86,19 +86,19 @@
 {
    struct chipset_power_state *ps = &power_state;
-	ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
-	ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
-	ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
-	ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
-	ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
-	ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
-	ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
-	ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
-	ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
-	ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
-	ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
-	ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
-	ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
+	ps->pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+	ps->pm1_en = inw(DEFAULT_PMBASE + PM1_EN);
+	ps->pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+	ps->tco1_sts = inw(DEFAULT_PMBASE + TCO1_STS);
+	ps->tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS);
+	ps->gpe0_sts[0] = inl(DEFAULT_PMBASE + GPE0_STS(0));
+	ps->gpe0_sts[1] = inl(DEFAULT_PMBASE + GPE0_STS(1));
+	ps->gpe0_sts[2] = inl(DEFAULT_PMBASE + GPE0_STS(2));
+	ps->gpe0_sts[3] = inl(DEFAULT_PMBASE + GPE0_STS(3));
+	ps->gpe0_en[0] = inl(DEFAULT_PMBASE + GPE0_EN(0));
+	ps->gpe0_en[1] = inl(DEFAULT_PMBASE + GPE0_EN(1));
+	ps->gpe0_en[2] = inl(DEFAULT_PMBASE + GPE0_EN(2));
+	ps->gpe0_en[3] = inl(DEFAULT_PMBASE + GPE0_EN(3));
ps->gen_pmcon1 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_1);
    ps->gen_pmcon2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2);
diff --git a/src/soc/intel/broadwell/pch/rcba.h b/src/soc/intel/broadwell/pch/rcba.h
index b514c6a..7293dff 100644
--- a/src/soc/intel/broadwell/pch/rcba.h
+++ b/src/soc/intel/broadwell/pch/rcba.h
@@ -5,9 +5,9 @@
#include <soc/intel/broadwell/memmap.h>
-#define RCBA8(x)	*((volatile u8 *)(RCBA_BASE_ADDRESS + x))
-#define RCBA16(x)	*((volatile u16 *)(RCBA_BASE_ADDRESS + x))
-#define RCBA32(x)	*((volatile u32 *)(RCBA_BASE_ADDRESS + x))
+#define RCBA8(x)	*((volatile u8 *)(DEFAULT_RCBA + x))
+#define RCBA16(x)	*((volatile u16 *)(DEFAULT_RCBA + x))
+#define RCBA32(x)	*((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
    RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c
index 8985905..76562ce 100644
--- a/src/soc/intel/broadwell/pch/smbus.c
+++ b/src/soc/intel/broadwell/pch/smbus.c
@@ -61,7 +61,7 @@
 static void smbus_read_resources(struct device *dev)
 {
    struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
-	res->base = SMBUS_BASE_ADDRESS;
+	res->base = CONFIG_FIXED_SMBUS_IO_BASE;
    res->size = 32;
    res->limit = res->base + res->size - 1;
    res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/soc/intel/broadwell/pch/smi.c
index 21986e3..3231f2c 100644
--- a/src/soc/intel/broadwell/pch/smi.c
+++ b/src/soc/intel/broadwell/pch/smi.c
@@ -14,9 +14,9 @@
    u32 smi_en;
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
-	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", DEFAULT_PMBASE);
-	smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
+	smi_en = inl(DEFAULT_PMBASE + SMI_EN);
    if (smi_en & APMC_EN) {
    	printk(BIOS_INFO, "SMI# handler already enabled?\n");
    	return;
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index d79082a..ec3f819 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -16,13 +16,13 @@
    pei_data->pei_version = PEI_VERSION;
    pei_data->board_type = BOARD_TYPE_ULT;
    pei_data->usbdebug = CONFIG(USBDEBUG);
-	pei_data->pciexbar = MCFG_BASE_ADDRESS;
-	pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+	pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
+	pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
    pei_data->ehcibar = EARLY_EHCI_BAR;
    pei_data->xhcibar = EARLY_XHCI_BAR;
    pei_data->gttbar = EARLY_GTT_BAR;
-	pei_data->pmbase = ACPI_BASE_ADDRESS;
-	pei_data->gpiobase = GPIO_BASE_ADDRESS;
+	pei_data->pmbase = DEFAULT_PMBASE;
+	pei_data->gpiobase = DEFAULT_GPIOBASE;
    pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
    pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
    pei_data->tx_byte = &send_to_console;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I473336a77179a3d1d26933f481abded49e9f0864
Gerrit-Change-Number: 46956
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    