[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Felix Held (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Subrata Banik.

Felix Held has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 11:

(2 comments)

File src/soc/intel/common/block/pmc/pmclib.c:

PS11:
> > are the gpe1 registers for the same event as the gpe0 register with the same number? the code usin […]

so i'd guess that it's not correct to use the identical mask pmc_enable_std_gpe and pmc_disable_std_gpe to enable/disable the GPE0 and GPE1

https://review.coreboot.org/c/coreboot/+/84104/comment/1b37ef77_afbebd8b?usp... :
PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */
             : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a)
             : {
             : 	return NULL;
             : }
             : 
             : /* disable the corresponding GPE1 bits based on standard GPE0 bits */
             : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask)
             : {
             : }
             : 
             : /* enable the corresponding GPE1 bits based on standard GPE0 bits */
             : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask)
             : {
             : }
> > are those weak functions needed? i'd assume that if a soc selects SOC_INTEL_COMMON_BLOCK_ACPI_HAVE […]

when a soc selects SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, it has to implement those 3 functions in the soc code; when a soc doesn't select SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, all calls of those functions get optimized out, so i don't think that there's the need to have a weak implementation of those