Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21671
Change subject: [WIP] sb/intel/i82371eb: Rework ACPI DSDT table ......................................................................
[WIP] sb/intel/i82371eb: Rework ACPI DSDT table
Enter a major ACPI table rework based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. Pulls in DSDT table for superios if one is defined (only winbond/w83977tf in this group of patches). To be pulled in by DSDTs of mainboards using this southbridge.
Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui buurin@gmail.com --- A src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/acpi/pirq.asl 2 files changed, 245 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21671/1
diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl new file mode 100644 index 0000000..9f3916c --- /dev/null +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker Nick.Barker9@btinternet.com + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * Copyright (C) 2017 Keith Hui buurin@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ +#include "southbridge/intel/i82371eb/i82371eb.h" + +// Intel LPC Bus Device - 0:4.0 +Device (PX40) +{ + Name(_ADR, 0x00040000) + OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) + Field (PIRQ, ByteAcc, NoLock, Preserve) + { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } +/* + * OEM BIOS for asus/p2b-ls reports mainboard resources here whereas + * ACPI programming of asus/p2b fills this in at runtime. + */ +#if 0 + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) + IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C, ) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) + IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) + }) + CreateByteField (BUF1, _Y06._MIN, PMLO) // _MIN: Minimum Base Address + CreateByteField (BUF1, 0x03, PMHI) + CreateByteField (BUF1, _Y06._MAX, PMRL) // _MAX: Maximum Base Address + CreateByteField (BUF1, 0x05, PMRH) + CreateByteField (BUF1, _Y07._MIN, SBLO) // _MIN: Minimum Base Address + CreateByteField (BUF1, 0x0B, SBHI) + CreateByteField (BUF1, _Y07._MAX, SBRL) // _MAX: Maximum Base Address + CreateByteField (BUF1, 0x0D, SBRH) + Store (_SB.PCI0.PX43.PM00, Local0) + And (Local0, 0xFE, PMLO) /* _SB_.PCI0.PX40.SYSR._CRS.PMLO */ + Store (_SB.PCI0.PX43.PM01, PMHI) /* _SB_.PCI0.PX40.SYSR._CRS.PMHI */ + Store (_SB.PCI0.PX43.SB00, Local0) + And (Local0, 0xFE, SBLO) /* _SB_.PCI0.PX40.SYSR._CRS.SBLO */ + Store (_SB.PCI0.PX43.SB01, SBHI) /* _SB_.PCI0.PX40.SYSR._CRS.SBHI */ + Store (PMLO, PMRL) /* _SB_.PCI0.PX40.SYSR._CRS.PMRL */ + Store (PMHI, PMRH) /* _SB_.PCI0.PX40.SYSR._CRS.PMRH */ + Store (SBLO, SBRL) /* _SB_.PCI0.PX40.SYSR._CRS.SBRL */ + Store (SBHI, SBRH) /* _SB_.PCI0.PX40.SYSR._CRS.SBRH */ + Return (BUF1) /* _SB_.PCI0.PX40.SYSR._CRS.BUF1 */ + } + } +#endif +/* If a superio (with DSDT table) is selected in mainboard Kconfig, + * include its ASL code here, otherwise declare a few basic devices + * that seems to be important for WinXP install. */ +#ifdef CONFIG_SUPERIO_WINBOND_W83977TF +#include "superio/winbond/w83977tf/acpi/superio.asl" +#else + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } +#endif + /* PNP Motherboard Resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + External(_CRS) /* Resource Template in SSDT */ + } + + /* 8259-compatible Programmable Interrupt Controller */ + Device (PIC) + { + Name (_HID, EisaId ("PNP0000") ) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, ) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, ) + IRQNoFlags () {2} + }) + } + + /* PC-class DMA Controller */ + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200") ) + Name (_CRS, ResourceTemplate () + { + DMA (Compatibility, BusMaster, Transfer8, ) {4} + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,) + IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,) + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,) + }) + } + + /* PC-class System Timer */ + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x0040,0x0040,0x01,0x04,) + IRQNoFlags () {0} + }) + } + + /* AT Real-Time Clock */ + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") ) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x0070,0x0070,0x01,0x04,) + IRQNoFlags () {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x0061,0x0061,0x01,0x01,) + }) + } + + /* x87-compatible Floating Point Processing Unit */ + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04") ) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x00F0,0x00F0,0x01,0x10,) + IRQNoFlags () {13} + }) + } + +} +/* Power management functions to allow ACPI reporting of + * PM and SMBus base port resources */ +Device (PX43) +{ + Name (_ADR, 0x00040003) // _ADR: Address + OperationRegion (IPMU, PCI_Config, PMBA, 0x02) + Field (IPMU, ByteAcc, NoLock, Preserve) + { + PM00, 8, + PM01, 8 + } + + OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) + Field (ISMB, ByteAcc, NoLock, Preserve) + { + SB00, 8, + SB01, 8 + } +} diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl index 6525e1e..e36a0ec 100644 --- a/src/southbridge/intel/i82371eb/acpi/pirq.asl +++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl @@ -12,16 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -Field (_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve) -{ - Offset (0x60), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, -} - Name(IRQB, ResourceTemplate(){ IRQ(Level,ActiveLow,Shared){15} }) @@ -69,7 +59,7 @@ } \ } \
-PCI_INTX_DEV(LNKA, PRTA, 1) -PCI_INTX_DEV(LNKB, PRTB, 2) -PCI_INTX_DEV(LNKC, PRTC, 3) -PCI_INTX_DEV(LNKD, PRTD, 4) +PCI_INTX_DEV(LNKA, _SB.PCI0.PX40.PIRA, 1) +PCI_INTX_DEV(LNKB, _SB.PCI0.PX40.PIRB, 2) +PCI_INTX_DEV(LNKC, _SB.PCI0.PX40.PIRC, 3) +PCI_INTX_DEV(LNKD, _SB.PCI0.PX40.PIRD, 4)
-
Keith Hui (Code Review)