Patch merged into coreboot/master: During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width.

the following patch was just integrated into master:
commit ba894be382c1a0365c435d5be2b54422731d66c8
Author: Timothy Pearson 
Date:   Thu Feb 25 23:20:14 2016 -0600

During DRAM initialization on certain ASpeed devices, an incorrect
    bit (bit 10) was checked in the "SDRAM Bus Width Status" register
    to determine DRAM width.

Query bit 6 instead in accordance with the Aspeed AST2050 datasheet
    v1.05.

Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/13807
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand 
    Reviewed-by: Stefan Reinauer

See https://review.coreboot.org/13807 for details.

-gerrit