Change in coreboot[master]: mb/google/brask: Correct SSD power sequence

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58045 )

Change subject: mb/google/brask: Correct SSD power sequence
......................................................................

mb/google/brask: Correct SSD power sequence

M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5

Signed-off-by: Eric Lai 
Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
1 file changed, 11 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
index b7d2985..777b816 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -369,6 +369,8 @@
 static const struct pad_config early_gpio_table[] = {
    /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
    /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
    PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
    /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
@@ -384,6 +386,8 @@
    PAD_CFG_GPO(GPP_D1, 0, DEEP),
    /* D2  : ISH_GP2 ==> EN_FP_PWR */
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_D11, 1, DEEP),
    /* E15 : RSVD_TP ==> PCH_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
    /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
@@ -394,6 +398,11 @@
    PAD_CFG_GPO(GPP_H13, 1, DEEP),
 };

+static const struct pad_config romstage_gpio_table[] = {
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+};
+
 const struct pad_config *__weak variant_gpio_table(size_t *num)
 {
    *num = ARRAY_SIZE(gpio_table);
@@ -425,6 +434,6 @@

const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
 {
-	*num = 0;
-	return NULL;
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
 }

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.