Attention is currently required from: Werner Zeh.
Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email )
Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ......................................................................
mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. The appropriate value was determined by using an oscilloscope.
Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/76175/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 1e7fa37..e47965a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -13,6 +13,8 @@ #include <baseboard/variants.h> #include <types.h>
+#define TX_DWORD3_P0 0xc8c + void variant_mainboard_final(void) { struct device *dev = NULL; @@ -32,6 +34,14 @@ */ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
+ /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3 on SATA port 0. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x5a sets the swing level to 0.7 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3_P0, (0x00 << 16), (0x5a << 16)); + /* Set Master Enable for on-board PCI device if allowed. */ dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0); if (dev) {