[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Hello Jincheng Li,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/84316?usp=email

to review the following change.

Change subject: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms
......................................................................

soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms

Change-Id: I0755143b21633d5fa8fe4a6eb93e4e6ff0301ab5
Signed-off-by: Jincheng Li 
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/84316/1

diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 9ba04fa..0e3fd8f 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -268,7 +268,7 @@

// Add DRHD Hardware Unit

-	if (is_dev_on_domain0(iommu)) {
+	if (!CONFIG(SOC_INTEL_COMMON_IBL_BASE) && is_dev_on_domain0(iommu)) {
    	printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
    		"Register Base Address: 0x%x\n",
    		DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base);