Patch merged into coreboot/master: 92da206 superio/winbond/w83627uhg: Depreciate romstage component

the following patch was just integrated into master:
commit 92da206532598bd0cec91b2cddc7a1296400d728
Author: Edward O'Callaghan 
Date:   Tue May 13 23:52:30 2014 +1000

superio/winbond/w83627uhg: Depreciate romstage component

Depreciate the model specific early_serial.c romstage component for this
    Super I/O in favor of the recent generic winbond romstage framework.

Convert dependent board to generic winbond serial init. Note the clock
    function is actually invalid since it never enters into PNP config mode
    to twiddle the register. Further, 48MHz is the default (page 9 of
    data-sheet) and so romstage.c need not do anything to the clock rate
    hence why it presumably works with this invalid function.

Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
    Signed-off-by: Edward O'Callaghan 
    Reviewed-on: http://review.coreboot.org/5725
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering

See http://review.coreboot.org/5725 for details.

-gerrit