Patch set updated for coreboot: Random x86_64 fixes from Scott

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11107

-gerrit

commit 0eff030a97dd8f520709a4412400c01fceff8352
Author: Stefan Reinauer <[e-mail]>
Date:   Fri Jul 31 16:44:03 2015 -0700

    Random x86_64 fixes from Scott
    
    Need to figure out what to do with these
    
    Change-Id: I6ed295131347796b27e660ccf3fca0de22801069
    Signed-off-by: Stefan Reinauer <[e-mail]>
    Signed-off-by: Scott Duplichan <[e-mail]>
---
 src/lib/ramstage.ld                                      | 3 ++-
 src/southbridge/amd/cimx/sb800/smbus_spd.c               | 2 +-
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S        | 5 +++++
 src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 8 ++++++++
 4 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld
index 432df40..c5719d6 100644
--- a/src/lib/ramstage.ld
+++ b/src/lib/ramstage.ld
@@ -59,6 +59,7 @@
 	cpu_drivers = . ;
 	KEEP(*(.rodata.cpu_driver));
 	ecpu_drivers = . ;
+	. = ALIGN(16);
 	_bs_init_begin = .;
 	KEEP(*(.bs_init));
 	LONG(0);
@@ -100,7 +101,7 @@
 	_heap = .;
 	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
 	. += CONFIG_HEAP_SIZE ;
-	. = ALIGN(4);
+	. = ALIGN(8);
 	_eheap = .;
 	_eramstage = .;
 	_eprogram = .;
diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c
index 1e458bd..052ee31 100644
--- a/src/southbridge/amd/cimx/sb800/smbus_spd.c
+++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c
@@ -100,7 +100,7 @@ static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
 					 UINT16 count)
 {
 	UINT16 index;
-	UINT8 status;
+	UINT8 status = 0;
 	UINT8 initial_offset = 0;
 
 	setupFch(iobase);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
index 48ee5d0..9701087 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
@@ -75,6 +75,11 @@ ExecuteFinalHltInstruction:
 
   bt $0,  %esi                     /* .if (esi & 1h) */
   jz  2f
+#ifdef __x86_64__
+  /* hack to protect cache as ram page tables until copied to memory */
+  jmp  7f
+#endif
+
     /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */
     movl %edi,  %esi                /* Get ApMtrrSettingList */
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
index ebcb58e..807a518 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
@@ -852,6 +852,10 @@ ApUtilSetupIdtForHlt (
   UINT64  HandlerOffset;
   UINT64  EferRegister;
   IDT_BASE_LIMIT IdtInfo;
+#ifdef __x86_64__
+  // old way doesn't work with the -Og build
+  static const UINT8 iretOpcode [] = {/*0xEB, 0xFE,*/ 0x48, 0xCF};  // iretq
+#endif
 
   LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader);
   if ((EferRegister & 0x100) != 0) {
@@ -860,7 +864,11 @@ ApUtilSetupIdtForHlt (
     DescSize = 8;
   }
 
+#ifdef __x86_64__
+  HandlerOffset = (UINT64) (intptr_t) &iretOpcode;
+#else
   HandlerOffset = (UINT64) (intptr_t) &NmiHandler;
+#endif
   NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF);
   NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF);
   GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);