[XS] Change in coreboot[master]: mb/google/brya/variants/hades: Set WP signal to GPP_E12

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75536?usp=email )

Change subject: mb/google/brya/variants/hades: Set WP signal to GPP_E12
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mb/google/brya/variants/hades: Set WP signal to GPP_E12

Move the WP signal to GPP_E12 from the current GPP_E15 to
match the design.

BUG=b:285084125
TEST=WP signal reports as we expect
Signed-off-by: Tarun Tuli 
Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/gpio.h
M src/mainboard/google/brya/variants/hades/gpio.c
2 files changed, 3 insertions(+), 5 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/gpio.h
index 6da54bf..b974aa5 100644
--- a/src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/hades/include/baseboard/gpio.h
@@ -12,7 +12,7 @@
 /* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
 #define GPE_EC_WAKE		GPE0_DW2_17
 /* WP signal to PCH */
-#define GPIO_PCH_WP		GPP_E15
+#define GPIO_PCH_WP		GPP_E12
 /* EC in RW or RO */
 #define GPIO_EC_IN_RW		GPP_F18
 /* Used to gate SoC's SLP_S0# signal */
diff --git a/src/mainboard/google/brya/variants/hades/gpio.c b/src/mainboard/google/brya/variants/hades/gpio.c
index 1c210e8..f826a65 100644
--- a/src/mainboard/google/brya/variants/hades/gpio.c
+++ b/src/mainboard/google/brya/variants/hades/gpio.c
@@ -403,17 +403,15 @@
    PAD_CFG_GPO(GPP_D2, 1, DEEP),
    /* GPP_D11 : [] ==> EN_PP3300_SSD */
    PAD_CFG_GPO(GPP_D11, 1, PLTRST),
+	/* GPP_E12 : [] ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
    /* GPP_E13 : [] ==> MEM_CH_SEL */
    PAD_CFG_GPI(GPP_E13, NONE, DEEP),
-	/* GPP_E15 : [] ==> PCH_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
    /* GPP_E16 : [] ==> WWAN_RST_L
     * To meet timing constrains - drive reset low.
     * Deasserted in ramstage.
     */
    PAD_CFG_GPO(GPP_E16, 0, DEEP),
-	/* GPP_E15 : [] ==> PCH_WP_OD */
-	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
    /* GPP_E18 : [] ==> EN_PP1800_GPU_X */
    PAD_CFG_GPO(GPP_E18, 0, PLTRST),
    /* GPP_F18 : [] ==> EC_IN_RW_OD */