[S] Change in coreboot[main]: mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83622?usp=email )

Change subject: mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs
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mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs

Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
---
M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
1 file changed, 15 insertions(+), 18 deletions(-)

Approvals:
  Matt DeVillier: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index ac3ebdc..c393019 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -1,33 +1,30 @@
 chip soc/intel/alderlake
-	# FSP Memory
-	register "enable_c6dram"		= "1"
-	register "sagv"				= "SaGv_Enabled"
-
-	# FSP Silicon
-	register "eist_enable"			= "1"
-	register "enable_c1e"			= "1"
-
-	register "disable_dynamic_tccold_handshake" = "1"
+	# FSP UPDs
+	register "disable_dynamic_tccold_handshake"	= "true"
+	register "eist_enable"				= "true"
+	register "enable_c1e"				= "true"
+	register "enable_c6dram"			= "true"
+	register "sagv"					= "SaGv_Enabled"

# Serial I/O
    register "serial_io_i2c_mode" = "{
-		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexI2C0]			= PchSerialIoPci,
    }"

register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0]		= PchSerialIoSkipInit,
+		[PchSerialIoIndexUART0]			= PchSerialIoSkipInit,
    }"

# Power
-	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
-	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
-	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
-	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+	register "pch_slp_s3_min_assertion_width"	= "2"		# 50ms
+	register "pch_slp_s4_min_assertion_width"	= "3"		# 1s
+	register "pch_slp_sus_min_assertion_width"	= "3"		# 500ms
+	register "pch_slp_a_min_assertion_width"	= "3"		# 2s

# PM Util
-	register "pmc_gpe0_dw0"			= "GPP_B"
-	register "pmc_gpe0_dw1"			= "GPP_C"
-	register "pmc_gpe0_dw2"			= "GPP_E"
+	register "pmc_gpe0_dw0"				= "GPP_B"
+	register "pmc_gpe0_dw1"				= "GPP_C"
+	register "pmc_gpe0_dw2"				= "GPP_E"

# Device Tree
    device domain 0 on