Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Nico Huber, Jamie Chen, Subrata Banik, Henry Sun, Paul Menzel, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 17:

(1 comment)

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/166e03a6_dcf1c129 
PS17, Line 212: 	params->CdClock = config->cd_clock ? config->cd_clock - 1 : 0xff;
> I guess there are 2 problems  […]

Here are the actual values used by/expected by JSL FSP:

```
CdClock 0: 172.8Mhz
CdClock 1: 180Mhz
CdClock 2: 192Mhz
CdClock 3: 307.2Mhz
CdClock 4: 312Mhz
CdClock 5: 552Mhz
CdClock 6: 556.8Mhz
CdClock 7: 648Mhz
CdClock 8: 652.8Mhz
CdClock:0xFF Program Max based on reference clock:- For 19.2MHz, 38.4MHz = 652.8 MHz. For 24MHz = 648MHz.
```

So the comment in the FSP header is definitely wrong.

However a comment here might help explain why the games are being played here (i.e., we intentionally want the default to be Auto (0xff), so we reserve
the `0` value here to mean auto instead, and shift the other values by 1)