Hello Taniya Das,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/40329
to review the following change.
Change subject: sc7180: clock: Define the UART frequency for QUPV3 ......................................................................
sc7180: clock: Define the UART frequency for QUPV3
The frequency to be used by UART client is 7.3728MHz, thus define it in the clock header to be used by the driver.
Tested: UART frequency request by client driver.
Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e Signed-off-by: Taniya Das tdas@codeaurora.org --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/40329/1
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 92b84b6..a6a0f6b 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -27,7 +27,7 @@
struct clock_config qup_cfg[] = { { - .hz = 7372800, + .hz = QUPV3_UART_SRC_HZ, .src = SRC_GPLL0_EVEN_300MHZ, .div = DIV(1), .m = 384, diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 8ffe52b..94233de 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -33,6 +33,7 @@ #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) +#define QUPV3_UART_SRC_HZ 7372800
#define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1
Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40329 )
Change subject: sc7180: clock: Define the UART frequency for QUPV3 ......................................................................
Patch Set 2:
Patch Set 1: Code-Review+2
This should be rebased to the front of the train so we can land it and use it in the UART driver.
Done
Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40329 )
Change subject: sc7180: clock: Define the UART frequency for QUPV3 ......................................................................
sc7180: clock: Define the UART frequency for QUPV3
The frequency to be used by UART client is 7.3728MHz, thus define it in the clock header to be used by the driver.
Tested: UART frequency request by client driver.
Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e Signed-off-by: Taniya Das tdas@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/40329 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/include/soc/clock.h 2 files changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index b6b6d46..56185ee 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -22,7 +22,7 @@
struct clock_config qup_cfg[] = { { - .hz = 7372800, + .hz = QUPV3_UART_SRC_HZ, .src = SRC_GPLL0_EVEN_300MHZ, .div = DIV(1), .m = 384, diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 2a8af28..25903fb 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -32,6 +32,7 @@ #define SRC_XO_HZ (19200 * KHz) #define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_MAIN_HZ (600 * MHz) +#define QUPV3_UART_SRC_HZ 7372800
#define SRC_XO_19_2MHZ 0 #define SRC_GPLL0_MAIN_600MHZ 1
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40329 )
Change subject: sc7180: clock: Define the UART frequency for QUPV3 ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/1/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2504 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2503 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2502 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : FAIL : https://lava.9esec.io/r/2501
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Julius Werner (Code Review)
-
Ravi kumar (Code Review)
-
Ravi Kumar Bokka (Code Review)