Change in coreboot[master]: amd/stoneyridge: Remove PSP BAR init from cpu init

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21492

Change subject: amd/stoneyridge: Remove PSP BAR init from cpu init
......................................................................

amd/stoneyridge: Remove PSP BAR init from cpu init

Remove the step of setting PSP BAR3 from cpu_dev_ops .init.  The
BAR is configured in romstage by AmdInitPost().

Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/model_15_init.c
1 file changed, 0 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/21492/1

diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index a46f322..631e89c 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -30,23 +30,6 @@
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>

-#include <amdlib.h>
-#include <PspBaseLib.h>
-
-void PSPProgBar3Msr(void *Buffer);
-
-void PSPProgBar3Msr(void *Buffer)
-{
-	u32 Bar3Addr;
-	u64 Tmp64;
-	/* Get Bar3 Addr */
-	Bar3Addr = PspLibPciReadPspConfig(0x20);
-	Tmp64 = Bar3Addr;
-	printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
-	LibAmdMsrWrite(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL);
-	LibAmdMsrRead(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL);
-}
-
 static void model_15_init(device_t dev)
 {
    printk(BIOS_DEBUG, "Model 15 Init.\n");
@@ -106,7 +89,6 @@
    }
    printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 #endif
-	PSPProgBar3Msr(NULL);

/* DisableCf8ExtCfg */
    msr = rdmsr(NB_CFG_MSR);