Change in coreboot[master]: soc/amd/cezanne: Add eSPI support - coreboot-gerrit

1 Mar 2021


      Attention is currently required from: Bao Zheng.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49965 )
Change subject: soc/amd/cezanne: Add eSPI support
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Patch Set 8:
(1 comment)
File src/soc/amd/cezanne/early_fch.c:
https://review.coreboot.org/c/coreboot/+/49965/comment/643f2697_49ff7ea4 
PS8, Line 37: SOC_AMD_COMMON_BLOCK_USE_ESPI
...
had another look in the PPR and it lists both LPC and eSPI as features of the FCH in chapter 1. […]
Thanks Felix.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f
Gerrit-Change-Number: 49965
Gerrit-PatchSet: 8
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