[M] Change in coreboot[master]: [NOT TESTED]{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure I...

[Johnny Lin (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Tim Chu.

Hello Arthur Heymans, Christian Walter, Tim Chu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76185?usp=email

to look at the new patch set (#2).

Change subject: [NOT TESTED]{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard
......................................................................

[NOT TESTED]{mb/intel/ac, soc/intel/xeon_sp/spr}: Let soc configure IIO UPDs from mainboard

Attempt to deduplicate mainboard mainboard_config_iio since there are
a few SPR-SP mainboards now.

Each mainboard needs to have a "include/sprsp_mb_iio.h" which defines its
mb_iio_table and mb_iio_bifur for IIO configurations, and soc common code
can configure IIO UPD from them.

This change removes initializing below UPD default non zero values,
so mainboard needs to make sure they are defined in its mb_iio_table:
PciePortConfig[socket].PcieMaxPayload[port] = 0x7;     /* Auto */
PciePortConfig[socket].DfxDnTxPresetGen3[port] = 0xff; /* Auto */

Not tested yet. Need to modfiy and verify other SPR mainboards,
and use DISPLAY_UPD_IIO_DATA to compare the results.

Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9
Signed-off-by: Johnny Lin 
---
R src/mainboard/intel/archercity_crb/include/sprsp_mb_iio.h
M src/mainboard/intel/archercity_crb/romstage.c
M src/soc/intel/xeon_sp/spr/Makefile.inc
M src/soc/intel/xeon_sp/spr/romstage.c
4 files changed, 79 insertions(+), 79 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/76185/2