Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85560?usp=email )
Change subject: soc/intel/xeon_sp: Move DFX and UNCORE PCI drivers ......................................................................
soc/intel/xeon_sp: Move DFX and UNCORE PCI drivers
Move the DFX and UNCORE PCI driver for 14nm Xeon-SP into own files under the 14nm subdirectory. Those are never needed on newer platforms and thus doesn't need to be compiled in.
TEST: Still boots on ocp/tiogapass.
Change-Id: Ie3d6cc11806669b8adf5041367cfbe36605612b1 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/14nm/Makefile.mk A src/soc/intel/xeon_sp/14nm/dfx.c A src/soc/intel/xeon_sp/14nm/uncore.c M src/soc/intel/xeon_sp/uncore.c 4 files changed, 75 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85560/1
diff --git a/src/soc/intel/xeon_sp/14nm/Makefile.mk b/src/soc/intel/xeon_sp/14nm/Makefile.mk index 4dd57d6..4717098 100644 --- a/src/soc/intel/xeon_sp/14nm/Makefile.mk +++ b/src/soc/intel/xeon_sp/14nm/Makefile.mk @@ -7,5 +7,6 @@
romstage-y += romstage.c ramstage-y += cpu.c soc_acpi.c iio_ioapic.c +ramstage-y += dfx.c uncore.c
endif ## CONFIG_SOC_INTEL_XEON_SP_14NM diff --git a/src/soc/intel/xeon_sp/14nm/dfx.c b/src/soc/intel/xeon_sp/14nm/dfx.c new file mode 100644 index 0000000..1897877 --- /dev/null +++ b/src/soc/intel/xeon_sp/14nm/dfx.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <security/intel/txt/txt.h> +#include <soc/pci_devs.h> + +static void iio_dfx_global_init(struct device *dev) +{ + if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown()) + return; + + uint16_t reg16; + pci_or_config16(dev, IIO_DFX_LCK_CTL, 0x3ff); + reg16 = pci_read_config16(dev, IIO_DFX_TSWCTL0); + reg16 &= ~(1 << 4); // allow ib mmio cfg + reg16 &= ~(1 << 5); // ignore acs p2p ma lpbk + reg16 |= (1 << 3); // me disable + pci_write_config16(dev, IIO_DFX_TSWCTL0, reg16); +} + +static const unsigned short iio_dfx_global_ids[] = { + 0x202d, + 0x203d, + 0 +}; + +static struct device_operations iio_dfx_global_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = iio_dfx_global_init, +}; + +static const struct pci_driver iio_dfx_global_driver __pci_driver = { + .ops = &iio_dfx_global_ops, + .vendor = PCI_VID_INTEL, + .devices = iio_dfx_global_ids, +}; diff --git a/src/soc/intel/xeon_sp/14nm/uncore.c b/src/soc/intel/xeon_sp/14nm/uncore.c new file mode 100644 index 0000000..208a78c --- /dev/null +++ b/src/soc/intel/xeon_sp/14nm/uncore.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <security/intel/txt/txt.h> +#include <soc/pci_devs.h> + +static void dmi3_init(struct device *dev) +{ + if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown()) + return; + /* Disable error injection */ + pci_or_config16(dev, ERRINJCON, 1 << 0); + + /* + * DMIRCBAR registers are not TXT lockable, but the BAR enable + * bit is. TXT requires that DMIRCBAR be disabled for security. + */ + pci_and_config32(dev, DMIRCBAR, ~(1 << 0)); +} + +static struct device_operations dmi3_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = dmi3_init, +}; + +static const struct pci_driver dmi3_driver __pci_driver = { + .ops = &dmi3_ops, + .vendor = PCI_VID_INTEL, + .device = DMI3_DEVID, +}; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 85e45db..d964310 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -442,65 +442,3 @@ .vendor = PCI_VID_INTEL, .devices = mmapvtd_ids }; - -static void dmi3_init(struct device *dev) -{ - if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown()) - return; - /* Disable error injection */ - pci_or_config16(dev, ERRINJCON, 1 << 0); - - /* - * DMIRCBAR registers are not TXT lockable, but the BAR enable - * bit is. TXT requires that DMIRCBAR be disabled for security. - */ - pci_and_config32(dev, DMIRCBAR, ~(1 << 0)); -} - -static struct device_operations dmi3_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = dmi3_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver dmi3_driver __pci_driver = { - .ops = &dmi3_ops, - .vendor = PCI_VID_INTEL, - .device = DMI3_DEVID, -}; - -static void iio_dfx_global_init(struct device *dev) -{ - if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown()) - return; - - uint16_t reg16; - pci_or_config16(dev, IIO_DFX_LCK_CTL, 0x3ff); - reg16 = pci_read_config16(dev, IIO_DFX_TSWCTL0); - reg16 &= ~(1 << 4); // allow ib mmio cfg - reg16 &= ~(1 << 5); // ignore acs p2p ma lpbk - reg16 |= (1 << 3); // me disable - pci_write_config16(dev, IIO_DFX_TSWCTL0, reg16); -} - -static const unsigned short iio_dfx_global_ids[] = { - 0x202d, - 0x203d, - 0 -}; - -static struct device_operations iio_dfx_global_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = iio_dfx_global_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver iio_dfx_global_driver __pci_driver = { - .ops = &iio_dfx_global_ops, - .vendor = PCI_VID_INTEL, - .devices = iio_dfx_global_ids, -};
-
Patrick Rudolph (Code Review)