[S] Change in coreboot[master]: soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66230 )

Change subject: soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC
......................................................................

soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC

The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes 
Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/apollolake/acpi/northbridge.asl
1 file changed, 23 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index f8023be..373d6b8 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -11,8 +11,12 @@
    OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
    Field (MCHP, DWordAcc, NoLock, Preserve)
    {
-		Offset(0x60),
-		MCNF,	32,	/* PCI MMCONF base */
+		Offset (0x60),	/* PCIEXBAR (0:0:0:60)
+		PXEN,	1,	/* Enable */
+		PXSZ,	2,	/* PCI Express Size */
+		    ,	25,
+		PXBR,	11,	/* PCI Express Base Address */
+
    	Offset (0xA8),
    	TUUD, 64,	/* Top of Upper Used Memory */
    	Offset(0xB4),