Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )

Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
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Patch Set 2:

(1 comment)

File src/soc/intel/common/block/cpu/mp_init.c:

https://review.coreboot.org/c/coreboot/+/62566/comment/04de3ba4_405ea25e 
PS2, Line 164: MP_SERVICES_PPI
> At least what I have heared from Sheng Alder Lake is affected, too.

Yeah sorry for late reply. I also observed the same thing from my side. I checked the MTRR output by coreboot where the memory for SPI was not there (maybe i missed some config?) and there was always some slow moment before entering to payload. With this changes it is resolved. Already asked Intel ADL team to help verify on their side.