[S] Change in coreboot[master]: soc/intel/alderlake: Disable PCIe clock gating

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons, Subrata Banik, Tarun Tuli.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76687?usp=email )

Change subject: soc/intel/alderlake: Disable PCIe clock gating
......................................................................

Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/76687/comment/1934f8ad_05aa88df :
PS1, Line 8:
> > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […]

Done

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/76687/comment/4dee682e_4aafa2b3 :
PS1, Line 925: PCIe PCH
> nit: PCH PCIe

Done