[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake

[Paul Menzel (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.

Paul Menzel has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )

Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
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Patch Set 66:

(6 comments)

Patchset:

PS66: 
How did you create the ASL files? Copy from some datasheet? Write from scratch?

Commit Message:

https://review.coreboot.org/c/coreboot/+/83772/comment/e55d4db5_79b2a50a?usp... :
PS66, Line 12: wake up
waking up or wakeup or wake-up

https://review.coreboot.org/c/coreboot/+/83772/comment/45185627_1ef34539?usp... :
PS66, Line 14: ,
Not needed.

https://review.coreboot.org/c/coreboot/+/83772/comment/cd4594e9_feec8213?usp... :
PS66, Line 16: gaurd
guard

https://review.coreboot.org/c/coreboot/+/83772/comment/8eb5f4a4_09c453d9?usp... :
PS66, Line 15:   common/block/acpi/acpi/northbridge.asl binding with PTL change,
             :   #if DMI_BASE_SIZE gaurd check is added in northbridge.asl
Indent with one more space to align with above.?

File src/soc/intel/pantherlake/acpi/tcss.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/356449d2_9d165da2?usp... :
PS66, Line 7: Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
            :  * USB device controller(xDCI)
Please add a space before (.