HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45616 )
Change subject: nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig ......................................................................
nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig
Change-Id: Id6daa380958ff9de3969abc4f0f53440067b464a Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/memmap.h M src/northbridge/intel/haswell/romstage.c 7 files changed, 12 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45616/1
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 84be33d..5152645 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -9,6 +9,10 @@
if NORTHBRIDGE_INTEL_HASWELL
+config DEFAULT_MCHBAR + hex + default 0xfed10000 + config HASWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT bool "Start verstage in bootblock" diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debf..243cb25 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -13,7 +13,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1d4eba6..e42c356 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b9c2c03 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -16,8 +16,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..a1125ab 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -28,9 +28,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index ac3b1db..2c1aa6a 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -7,7 +7,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eb..f922e68 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -47,7 +47,7 @@
struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45616 )
Change subject: nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45616
to look at the new patch set (#2).
Change subject: nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig ......................................................................
nb/intel/haswell: Move DEFAULT_MCHBAR to Kconfig
Change-Id: Id6daa380958ff9de3969abc4f0f53440067b464a Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/memmap.h 2 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45616/2
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45616
to look at the new patch set (#3).
Change subject: nb/intel/haswell: Move DEFAULT_BARs to Kconfig ......................................................................
nb/intel/haswell: Move DEFAULT_BARs to Kconfig
Change-Id: Id6daa380958ff9de3969abc4f0f53440067b464a Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/memmap.h 2 files changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45616/3
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45616 )
Change subject: nb/intel/haswell: Move DEFAULT_BARs to Kconfig ......................................................................
Abandoned
see 45613