[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................

Patch Set 10:

(4 comments)

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/f6b5d584_8d6ddd2b?usp... :
PS7, Line 25: #if !CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)
            : 
            : /* NOTE: For platform doesn't have support for GPE1, adding dummy entries here for common code
            :  */
            : #ifndef GPE1_STS
            : #define GPE1_STS(x) (0x0 + ((x) * 4))
            : #endif
            : #ifndef GPE1_REG_MAX
            : #define GPE1_REG_MAX 0
            : #endif
            : 
            : #endif
> correction: https://review.coreboot. […]

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/8573b4bf_b5fad821?usp... :
PS7, Line 341: pmc_clear_gpi_gpe0_status
> sure. Let me put them back.

Done

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/dbcd8f17_dfea1caf?usp... :
PS8, Line 321: 	soc_pmc_disable_std_gpe1(mask);
> > The only thing left is that if the EN bit(s) have been set prior to going to suspend. […]

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/0d0e42ea_bc78aee8?usp... :
PS8, Line 330: 	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1))
> same reason for pmc_disable_std_gpe()

Done