Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1

[Subrata Banik (Code Review)]

Attention is currently required from: Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian.
Hello Wonkyu Kim, build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/61457

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1
......................................................................

soc/intel/tigerlake: Use PMC IPC to disable HECI1

This patch allows common CSE block to make HECI1 function disable using
PMC IPC command `0xA9`.

Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
tigerlake to disable HECI1 device using PMC IPC.

Additionally, drop HECI_DISABLE_USING_SMM config from TGL SoC as HECI1
disabling using PMC IPC is more scalable as it can operate outside SMM.

BUG=none
TEST=None

Signed-off-by: Subrata Banik 
Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/smihandler.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/3