Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63785 )
Change subject: soc/intel/alderlake/acpi: Add ADL-S devices ......................................................................
soc/intel/alderlake/acpi: Add ADL-S devices
Add PCIe Root Ports, USB ports, GPIO Controller and SIO devices for ADL-S chipset.
Add IRQ routing tables for PCIe Root ports up to 28th.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c --- A src/soc/intel/alderlake/acpi/gpio_pch_s.asl M src/soc/intel/alderlake/acpi/pcie.asl M src/soc/intel/alderlake/acpi/serialio.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/alderlake/acpi/xhci.asl 5 files changed, 492 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63785/1
diff --git a/src/soc/intel/alderlake/acpi/gpio_pch_s.asl b/src/soc/intel/alderlake/acpi/gpio_pch_s.asl new file mode 100644 index 0000000..f6a3226 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/gpio_pch_s.asl @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> +#include <soc/gpio_defs_pch_s.h> +#include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 3 */ + If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END) + { + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPIO_COM3_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_3) { + Local0 = PID_GPIOCOM3 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index f2123aa..201da05 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -54,7 +54,7 @@
Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13, 17, 21, 25 }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +62,7 @@ } }
- Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14, 18, 22, 26 }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +70,7 @@ } }
- Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15, 19, 23, 27 }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +78,7 @@ } }
- Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16, 20, 24, 28 }) { If (PICM) { Return (IQDA) } Else { @@ -300,6 +300,296 @@ } }
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP25) +{ + Name (_ADR, 0x001A0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP26) +{ + Name (_ADR, 0x001A0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP27) +{ + Name (_ADR, 0x001A0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP28) +{ + Name (_ADR, 0x001A0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (PEG0) +{ + Name (_ADR, 0x00060000) +} + +Device (PEG2) +{ + Name (_ADR, 0x00010000) +} + +Device (PEG3) +{ + Name (_ADR, 0x00010001) +} +#endif + + #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) Device (PEG0) { diff --git a/src/soc/intel/alderlake/acpi/serialio.asl b/src/soc/intel/alderlake/acpi/serialio.asl index a325953..93632fc 100644 --- a/src/soc/intel/alderlake/acpi/serialio.asl +++ b/src/soc/intel/alderlake/acpi/serialio.asl @@ -91,3 +91,9 @@ Name (_ADR, 0x00190002) Name (_DDN, "Serial IO UART Controller 2") } + +Device (UAR3) +{ + Name (_ADR, 0x00110000) + Name (_DDN, "Serial IO UART Controller 3") +} diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 3c37d57..57fc401 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -12,7 +12,11 @@ #include "camera_clock_ctl.asl"
/* GPIO controller */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#include "gpio_pch_s.asl" +#else #include "gpio.asl" +#endif
/* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index 9c70d3f..34ff612 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -23,7 +23,40 @@ {
} +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + /* Root Hub for Alder Lake-P PCH */ + Device (RHUB) + { + Name (_ADR, Zero)
+ /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + Device (HS11) { Name (_ADR, 11) } + Device (HS12) { Name (_ADR, 12) } + Device (HS13) { Name (_ADR, 13) } + Device (HS14) { Name (_ADR, 14) } + /* USB3 */ + Device (SS01) { Name (_ADR, 15) } + Device (SS02) { Name (_ADR, 16) } + Device (SS03) { Name (_ADR, 17) } + Device (SS04) { Name (_ADR, 18) } + Device (SS05) { Name (_ADR, 19) } + Device (SS06) { Name (_ADR, 20) } + Device (SS07) { Name (_ADR, 21) } + Device (SS08) { Name (_ADR, 22) } + Device (SS09) { Name (_ADR, 23) } + Device (SS10) { Name (_ADR, 24) } + } +#else /* Root Hub for Alder Lake-P PCH */ Device (RHUB) { @@ -46,4 +79,5 @@ Device (SS03) { Name (_ADR, 13) } Device (SS04) { Name (_ADR, 14) } } +#endif }
-
Michał Żygowski (Code Review)