Sowmya Aralguppe has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83890?usp=email )
Change subject: amend ......................................................................
amend
Change-Id: I5de03cd79b07d04559fcc33d007c1a9eae9fb693 --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/83890/1
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 1a52057..7d029fc 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -356,7 +356,8 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
/* If battery is not present - Boot with maximum non-turbo frequency */ - if (CONFIG(EC_GOOGLE_CHROMEEC) && (!google_chromeec_is_battery_present_and_above_critical_threshold())) { + if (CONFIG(EC_GOOGLE_CHROMEEC) && + (!google_chromeec_is_battery_present_and_above_critical_threshold())) { /* Sets the boot frequency starting from reset vector: * 0: Maximum battery performance. * 1: Maximum non-turbo performance.