Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41890 )
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2.
BUG=b:143539650 TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41890/1
diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 0aebf8f..18b5a6c 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -22,6 +22,7 @@ DEFAULT_TRIP_POINT = 0xFFFFFFFFull, DEFAULT_WEIGHT = 100, DPTF_MAX_ART_THRESHOLDS = 10, + PPCC_REVISION = 2, };
/* Convert degrees C to 1/10 degree Kelvin for ACPI */ @@ -416,3 +417,46 @@ acpigen_pop_len(); /* Package */ acpigen_pop_len(); /* Scope */ } + +void dptf_write_power_limits(const struct dptf_power_limits *limits) +{ + char *pkg_count; + + /* Nothing to do */ + if (!limits->pl1.min_power && !limits->pl2.min_power) + return; + + dptf_write_scope(DPTF_CPU); + acpigen_write_method("PPCC", 0); + + pkg_count = acpigen_write_package(1); /* 1 for the Revision */ + acpigen_write_integer(PPCC_REVISION); /* revision */ + + if (limits->pl1.min_power) { + (*pkg_count)++; + acpigen_write_package(6); + acpigen_write_integer(0); /* PL1_INDEX */ + acpigen_write_integer(limits->pl1.min_power); + acpigen_write_integer(limits->pl1.max_power); + acpigen_write_integer(limits->pl1.time_window_min); + acpigen_write_integer(limits->pl1.time_window_max); + acpigen_write_integer(limits->pl1.granularity); + acpigen_pop_len(); /* inner Package */ + } + + if (limits->pl2.min_power) { + (*pkg_count)++; + acpigen_write_package(6); + acpigen_write_integer(1); /* PL2_INDEX */ + acpigen_write_integer(limits->pl1.min_power); + acpigen_write_integer(limits->pl1.max_power); + acpigen_write_integer(limits->pl1.time_window_min); + acpigen_write_integer(limits->pl1.time_window_max); + acpigen_write_integer(limits->pl1.granularity); + acpigen_pop_len(); /* inner Package */ + } + + acpigen_pop_len(); /* outer Package */ + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index cffc74d..5ea32d9 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -17,6 +17,7 @@ struct { struct dptf_charger_perf charger_perf[DPTF_MAX_CHARGER_PERF_STATES]; struct dptf_fan_perf fan_perf[DPTF_MAX_FAN_PERF_STATES]; + struct dptf_power_limits power_limits; } controls; };
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index c075ef1..70af050 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -76,6 +76,7 @@ /* Controls */ dptf_write_charger_perf(config->controls.charger_perf, DPTF_MAX_CHARGER_PERF_STATES); dptf_write_fan_perf(config->controls.fan_perf, DPTF_MAX_FAN_PERF_STATES); + dptf_write_power_limits(&config->controls.power_limits);
printk(BIOS_INFO, "\_SB.DPTF: %s at %s\n", dev->chip_ops->name, dev_path(dev)); } diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index dd608d3..33a9961 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -110,6 +110,26 @@ uint16_t power; };
+/* Running Average Power Limits (RAPL) */ +struct dptf_power_limit_config { + /* Minimum level of power limit, in mW */ + uint32_t min_power; + /* Maximum level of power limit, in mW */ + uint32_t max_power; + /* Minimum time window running average is over, in seconds */ + uint32_t time_window_min; + /* Maximum time window running average is over, in seconds */ + uint32_t time_window_max; + /* Granularity of the power limit setting (between min and max), in mW */ + uint16_t granularity; +}; + +/* Only PL1 and PL2 are controllable via DPTF */ +struct dptf_power_limits { + struct dptf_power_limit_config pl1; + struct dptf_power_limit_config pl2; +}; + /* * This function writes out _SB.DPTF.IDSP, which describes the different DPTF policies that * this implementation is using. @@ -155,6 +175,13 @@ */ void dptf_write_fan_perf(const struct dptf_fan_perf *perf, int max_count);
+/* + * This function writes out a PPCC table, which indicates power ranges that different Intel + * RAPLs can take, as well as the time period they average over and the minimum adjustment + * amount. + */ +void dptf_write_power_limits(const struct dptf_power_limits *limits); + /* Helper method to open the scope for a given participant. */ void dptf_write_scope(enum dptf_participant participant);
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41890
to look at the new patch set (#4).
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2.
BUG=b:143539650 TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41890/4
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Sumeet R Pawnikar, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41890
to look at the new patch set (#6).
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2.
BUG=b:143539650 TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41890/6
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Sumeet R Pawnikar, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41890
to look at the new patch set (#8).
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2.
BUG=b:143539650 TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41890/8
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41890 )
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41890/10/src/acpi/acpigen_dptf.c File src/acpi/acpigen_dptf.c:
https://review.coreboot.org/c/coreboot/+/41890/10/src/acpi/acpigen_dptf.c@39... PS10, Line 390: pl1 should these all be pl2?
https://review.coreboot.org/c/coreboot/+/41890/10/src/include/acpi/acpigen_d... File src/include/acpi/acpigen_dptf.h:
https://review.coreboot.org/c/coreboot/+/41890/10/src/include/acpi/acpigen_d... PS10, Line 167: RAPLs maybe define RAPL here
Hello build bot (Jenkins), Furquan Shaikh, Duncan Laurie, Sumeet R Pawnikar, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41890
to look at the new patch set (#11).
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2.
BUG=b:143539650 TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/41890/11
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41890 )
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41890/10/src/acpi/acpigen_dptf.c File src/acpi/acpigen_dptf.c:
https://review.coreboot.org/c/coreboot/+/41890/10/src/acpi/acpigen_dptf.c@39... PS10, Line 390: pl1
should these all be pl2?
Whoops, copy-pasta strikes again.
https://review.coreboot.org/c/coreboot/+/41890/10/src/include/acpi/acpigen_d... File src/include/acpi/acpigen_dptf.h:
https://review.coreboot.org/c/coreboot/+/41890/10/src/include/acpi/acpigen_d... PS10, Line 167: RAPLs
maybe define RAPL here
Ack
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41890 )
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
Patch Set 13: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41890 )
Change subject: dptf: Add support for Running Average Power Limits ......................................................................
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2.
BUG=b:143539650 TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 75 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 6caf8bf..9be3f5b 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -15,6 +15,9 @@ DEFAULT_TRIP_POINT = 0xFFFFFFFFull, DEFAULT_WEIGHT = 100, DPTF_MAX_ART_THRESHOLDS = 10, + PPCC_REVISION = 2, + RAPL_PL1_INDEX = 0, + RAPL_PL2_INDEX = 1, };
/* Convert degrees C to 1/10 degree Kelvin for ACPI */ @@ -358,3 +361,46 @@ acpigen_pop_len(); /* Package */ acpigen_pop_len(); /* Scope */ } + +void dptf_write_power_limits(const struct dptf_power_limits *limits) +{ + char *pkg_count; + + /* Nothing to do */ + if (!limits->pl1.min_power && !limits->pl2.min_power) + return; + + dptf_write_scope(DPTF_CPU); + acpigen_write_method("PPCC", 0); + + pkg_count = acpigen_write_package(1); /* 1 for the Revision */ + acpigen_write_integer(PPCC_REVISION); /* revision */ + + if (limits->pl1.min_power) { + (*pkg_count)++; + acpigen_write_package(6); + acpigen_write_integer(RAPL_PL1_INDEX); + acpigen_write_integer(limits->pl1.min_power); + acpigen_write_integer(limits->pl1.max_power); + acpigen_write_integer(limits->pl1.time_window_min); + acpigen_write_integer(limits->pl1.time_window_max); + acpigen_write_integer(limits->pl1.granularity); + acpigen_pop_len(); /* inner Package */ + } + + if (limits->pl2.min_power) { + (*pkg_count)++; + acpigen_write_package(6); + acpigen_write_integer(RAPL_PL2_INDEX); + acpigen_write_integer(limits->pl2.min_power); + acpigen_write_integer(limits->pl2.max_power); + acpigen_write_integer(limits->pl2.time_window_min); + acpigen_write_integer(limits->pl2.time_window_max); + acpigen_write_integer(limits->pl2.granularity); + acpigen_pop_len(); /* inner Package */ + } + + acpigen_pop_len(); /* outer Package */ + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index cc4ae47..0d2c25c 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -15,6 +15,7 @@ struct { struct dptf_charger_perf charger_perf[DPTF_MAX_CHARGER_PERF_STATES]; struct dptf_fan_perf fan_perf[DPTF_MAX_FAN_PERF_STATES]; + struct dptf_power_limits power_limits; } controls; };
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index bfc0420..15a7d12 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -75,6 +75,7 @@ /* Controls */ dptf_write_charger_perf(config->controls.charger_perf, DPTF_MAX_CHARGER_PERF_STATES); dptf_write_fan_perf(config->controls.fan_perf, DPTF_MAX_FAN_PERF_STATES); + dptf_write_power_limits(&config->controls.power_limits);
printk(BIOS_INFO, "\_SB.DPTF: %s at %s\n", dev->chip_ops->name, dev_path(dev)); } diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 3452f79..474f72c 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -103,6 +103,26 @@ uint16_t power; };
+/* Running Average Power Limits (RAPL) */ +struct dptf_power_limit_config { + /* Minimum level of power limit, in mW */ + uint32_t min_power; + /* Maximum level of power limit, in mW */ + uint32_t max_power; + /* Minimum time window running average is over, in seconds */ + uint32_t time_window_min; + /* Maximum time window running average is over, in seconds */ + uint32_t time_window_max; + /* Granularity of the power limit setting (between min and max), in mW */ + uint16_t granularity; +}; + +/* Only PL1 and PL2 are controllable via DPTF */ +struct dptf_power_limits { + struct dptf_power_limit_config pl1; + struct dptf_power_limit_config pl2; +}; + /* * This function provides tables of temperature and corresponding fan or percent. When the * temperature thresholds are met (_AC0 - _AC9), the fan is driven to corresponding percentage @@ -142,6 +162,13 @@ */ void dptf_write_fan_perf(const struct dptf_fan_perf *perf, int max_count);
+/* + * This function writes out a PPCC table, which indicates power ranges that different Intel + * Running Average Power Limits (RAPLs) can take, as well as the time period they average over + * and the minimum adjustment amount. + */ +void dptf_write_power_limits(const struct dptf_power_limits *limits); + /* Helper method to open the scope for a given participant. */ void dptf_write_scope(enum dptf_participant participant);