Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63615 )

Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock
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intel/common/../systemagent: Enable MCHBAR in bootblock

MCHBAR is enabled from romstage but GPMR drvier via IOC(IO Cache)
uses MCHBAR in bootblock.
So, we need to enable MCHBAR early as possible.

TEST=boot to OS in TGL RVP and MTL PSS
Signed-off-by: Wonkyu Kim 
Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb
---
M src/soc/intel/common/block/systemagent/systemagent_early.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63615/1

diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index a77b307..1927ea5 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -20,6 +20,9 @@
 {
    uint32_t reg;
    uint8_t pciexbar_length;
+	static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+	};

/*
     * The PCIEXBAR is assumed to live in the memory mapped IO space under
@@ -53,6 +56,10 @@
     * to avoid power on default non-zero value (if any).
     */
    pci_write_config32(SA_DEV_ROOT, TSEG, 0);
+
+	/* Enable MCHBAR */
+	sa_set_pci_bar(soc_fixed_pci_resources,
+			ARRAY_SIZE(soc_fixed_pci_resources));
 }

void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,