Patch set updated for coreboot: e6abc5c intel/bd82x6x: Rename SATA speed "support" register to "limit"
Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4777
-gerrit
commit e6abc5c5222ab48877f01ccb56b8dacac36823e9 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Tue Jan 21 18:31:35 2014 -0600
intel/bd82x6x: Rename SATA speed "support" register to "limit"
"sata_interface_speed_support" implies that we must tell coreboot, via devicetree.cb at what speed the SATA ports can operate. However, that is not necessary, and the actual use of this register is to limit the speed of all ports connected to the PCH. As such, use "sata_interface_speed_limit" as a better name.
Change-Id: Icb07644d7bb044687b6b571bee6e2bde7f4cab85 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/mainboard/google/butterfly/devicetree.cb | 2 +- src/mainboard/google/stout/devicetree.cb | 2 +- src/mainboard/kontron/ktqm77/devicetree.cb | 2 +- src/mainboard/lenovo/x230/devicetree.cb | 2 +- src/southbridge/intel/bd82x6x/chip.h | 16 +++++++++++----- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- 7 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9a7a1d5..36f3ba3 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2" + register "sata_interface_speed_limit" = "0x2"
# Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 653d3fe..e157035 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2" + register "sata_interface_speed_limit" = "0x2"
# Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index f6390ac..c850609 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) - register "sata_interface_speed_support" = "0x3" + register "sata_interface_speed_limit" = "0x3"
# TODO: Enable generic LPC decodes... register "gen1_dec" = "0x001c02e1" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 3650b38..aebd915 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" + register "sata_interface_speed_limit" = "0x3"
register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0f2f0e9..c722da5 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -69,15 +69,21 @@ struct southbridge_intel_bd82x6x_config { uint32_t sata_port1_gen3_tx;
/** - * SATA Interface Speed Support Configuration + * SATA Interface Speed Support Configuration (ISS) + * + * This option limits the maximum SATA link speed on all SATA ports. + * For systems with a mix of 6G and 3G ports, each port will operate up + * to its capability, but not any higher than the limit set here. This + * option should only be used if the SATA port cannot operate at its + * full speed due to hardware bugs, such as board mis-routing. * * Only the lower two bits have a meaning: * 00 - No effect (leave as chip default) - * 01 - 1.5 Gb/s maximum speed - * 10 - 3.0 Gb/s maximum speed - * 11 - 6.0 Gb/s maximum speed + * 01 - 1.5 Gb/s maximum speed (Gen 1) + * 10 - 3.0 Gb/s maximum speed (Gen 2) + * 11 - 6.0 Gb/s maximum speed (Gen 3) */ - uint8_t sata_interface_speed_support; + uint8_t sata_interface_speed_limit;
uint32_t gen1_dec; uint32_t gen2_dec; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 133ebee..8d12202 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -107,10 +107,10 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ - if (config->sata_interface_speed_support) + if (config->sata_interface_speed_limit) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) + reg32 |= (config->sata_interface_speed_limit & 0x03) << 20; } write32(abar + 0x00, reg32); diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 078dc8e..2a6e454 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -110,9 +110,9 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ - if (config->sata_interface_speed_support) { + if (config->sata_interface_speed_limit) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) + reg32 |= (config->sata_interface_speed_limit & 0x03) << 20; } write32(abar + 0x00, reg32);
-
Alexandru Gagniuc