[M] Change in coreboot[master]: soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOAD

[David Hendricks (Code Review)]

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans.

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71144 )

Change subject: soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOAD
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Patch Set 1: Code-Review-1

(1 comment)

File src/soc/intel/xeon_sp/finalize.c:

https://review.coreboot.org/c/coreboot/+/71144/comment/ac75d91b_8e116f82 
PS1, Line 47: 	if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
            : 		/* Set MSR_PPIN_CTL ENABLE to 1 */
            : 		msr.lo |= MSR_PPIN_CTL_ENABLE;
            : 		wrmsr(MSR_PPIN_CTL, msr);
            : 	}
Is this needed? MSR_PPIN_CTL_ENABLE gets cleared in the next few lines.

Also, the description for the LockOut bit in the IA64/32 SDM says:
> If 1, indicates that further writes to MSR_PPIN_CTL is
> disallowed. Writing 1 to this bit is only permitted if the
> Enable_PPIN bit is clear.

I don't see a reason the Enable bit should be set here. Maybe it was intended to be set before rdmsr() above?