New subject: Change in coreboot[master]: mainboard/prodrive/hermes: Add new mainboard port

9 Jan 2020

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38303 )
Change subject: mainboard/prodrive/hermes: Add Support for Prodrive Hermes Board
......................................................................
mainboard/prodrive/hermes: Add Support for Prodrive Hermes Board
This patch adds support for the Prodrive Hermes mainboard. This is
untested yet.
Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter christian.walter@9elements.com
---
A src/mainboard/prodrive/Kconfig
A src/mainboard/prodrive/Kconfig.name
A src/mainboard/prodrive/hermes/Kconfig
A src/mainboard/prodrive/hermes/Kconfig.name
A src/mainboard/prodrive/hermes/Makefile.inc
A src/mainboard/prodrive/hermes/acpi_tables.c
A src/mainboard/prodrive/hermes/board_info.txt
A src/mainboard/prodrive/hermes/bootblock.c
A src/mainboard/prodrive/hermes/devicetree.cb
A src/mainboard/prodrive/hermes/dsdt.asl
A src/mainboard/prodrive/hermes/memory.c
A src/mainboard/prodrive/hermes/ramstage.c
A src/mainboard/prodrive/hermes/romstage.c
A src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc
A src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
A src/mainboard/prodrive/hermes/variants/baseboard/gpio.c
A src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h
A src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h
A src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
19 files changed, 993 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/38303/1

diff --git a/src/mainboard/prodrive/Kconfig b/src/mainboard/prodrive/Kconfig
new file mode 100644
index 0000000..0847425
--- /dev/null
+++ b/src/mainboard/prodrive/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_PRODRIVE
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/prodrive/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/prodrive/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Prodrive"
+
+endif # VENDOR_PRODRIVE
diff --git a/src/mainboard/prodrive/Kconfig.name b/src/mainboard/prodrive/Kconfig.name
new file mode 100644
index 0000000..b516ef1
--- /dev/null
+++ b/src/mainboard/prodrive/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_PRODRIVE
+	bool "Prodrive"
diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig
new file mode 100644
index 0000000..8d01923
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/Kconfig
@@ -0,0 +1,71 @@
+config BOARD_PRODRIVE_HERMES
+	def_bool n
+	select SOC_INTEL_COFFEELAKE
+	select BOARD_ROMSIZE_KB_32768
+	select GENERIC_SPD_BIN
+#	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SUPERIO_ASPEED_COMMON_PRE_RAM
+	select SUPERIO_ASPEED_AST2400
+	select DRIVERS_ASPEED_AST_COMMON
+	select DRIVERS_ASPEED_AST2050
+	select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
+	select IPMI_KCS
+	select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
+
+if BOARD_PRODRIVE_HERMES
+
+config MAINBOARD_FAMILY
+	string
+	default "PRODRIVE_HERMES_SERIES"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Baseboard"	if BOARD_PRODRIVE_HERMES_BASEBOARD
+
+config MAINBOARD_DIR
+	string
+	default "prodrive/hermes"
+
+config VARIANT_DIR
+	string
+	default "baseboard"	if BOARD_PRODRIVE_HERMES_BASEBOARD
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Baseboard"	if BOARD_PRODRIVE_HERMES_BASEBOARD
+
+config MAINBOARD_VENDOR
+	string
+	default "Prodrive"
+
+config MAX_CPUS
+	int
+	default 12
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config CONSOLE_POST
+	bool
+	default n
+
+config POST_DEVICE
+	bool
+	default n
+
+config POST_IO
+	bool
+	default n
+
+config CBFS_SIZE
+	hex
+	default 0xa00000
+
+endif # BOARD_PRODRIVE_HERMES
diff --git a/src/mainboard/prodrive/hermes/Kconfig.name b/src/mainboard/prodrive/hermes/Kconfig.name
new file mode 100644
index 0000000..034c285
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_PRODRIVE_HERMES_BASEBOARD
+	bool "Hermes"
+	select BOARD_PRODRIVE_HERMES
diff --git a/src/mainboard/prodrive/hermes/Makefile.inc b/src/mainboard/prodrive/hermes/Makefile.inc
new file mode 100644
index 0000000..073acc2
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/prodrive/hermes/variants/$(VARIANT_DIR)/include
+
+bootblock-y += bootblock.c
+romstage-y += memory.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/prodrive/hermes/acpi_tables.c b/src/mainboard/prodrive/hermes/acpi_tables.c
new file mode 100644
index 0000000..3b44754
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/acpi_tables.c
@@ -0,0 +1 @@
+/* Nothing here */
diff --git a/src/mainboard/prodrive/hermes/board_info.txt b/src/mainboard/prodrive/hermes/board_info.txt
new file mode 100644
index 0000000..84007b8
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/board_info.txt
@@ -0,0 +1,2 @@
+Category: server
+Vendor name: Prodrive
diff --git a/src/mainboard/prodrive/hermes/bootblock.c b/src/mainboard/prodrive/hermes/bootblock.c
new file mode 100644
index 0000000..9677536
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/bootblock.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/gpio.h>
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <superio/aspeed/common/aspeed.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <delay.h>
+#include <console/uart.h>
+#include <console/console.h>
+
+static void early_config_gpio(void)
+{
+	/* This is a hack for FSP because it does things in MemoryInit()
+	 * which it shouldn't do. We have to prepare certain gpios here
+	 * because of the brokenness in FSP. */
+	size_t num = 0;
+	const struct pad_config *early_gpio_table = get_early_gpio_table(&num);
+
+	gpio_configure_pads(early_gpio_table, num);
+}
+
+static void early_config_superio(void)
+{
+	const pnp_devfn_t serial_dev = PNP_DEV(0x4e, AST2400_SUART1);
+	if (CONFIG(CONSOLE_SERIAL)) {
+		aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+		/* The serial output is garbeled before this timeout.
+		 * FIXME: Find out why and remove delay.
+		 */
+		mdelay(1000);
+	}
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	early_config_gpio();
+	early_config_superio();
+}
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
new file mode 100644
index 0000000..b7321ac
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -0,0 +1,58 @@
+chip soc/intel/cannonlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 04.0 on  end # Intel Xeon E3
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 16.0 on  end # Management Engine Interface
+		device pci 16.1 on  end # Management Engine Interface
+		device pci 16.4 on  end # Management Engine Interface
+		device pci 17.0 on  end # SATA
+		device pci 1c.1 on  end # Aspeed Graphics
+		device pci 1e.0 on  end # UART #0
+		device pci 1f.0 on 	# LPC Interface
+			chip drivers/ipmi
+				# On cold boot it takes a while for the BMC to start the IPMI service
+				register "wait_for_bmc" = "0"
+				register "bmc_boot_timeout" = "60"
+				device pnp ca2.0 on end	# IPMI KCS
+			end
+			chip superio/common
+				device pnp 4e.0 on
+					chip superio/aspeed/ast2400
+						device pnp 4e.2 on	# SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 4e.3 on	# SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 4e.4 off end # SWC
+						device pnp 4e.5 off end # KBC
+						device pnp 4e.7 off end # GPIO
+						device pnp 4e.b off end # SUART3
+						device pnp 4e.c off end # SUART4
+						device pnp 4e.d off end # iLPC2AHB
+						device pnp 4e.e off end # Mailbox
+					end
+				end
+			end
+		end
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+	end
+
+end
diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl
new file mode 100644
index 0000000..e03bec1
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/dsdt.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2018 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	Scope (_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/cannonlake/acpi/northbridge.asl>
+			#include <soc/intel/cannonlake/acpi/southbridge.asl>
+		}
+	}
+
+	// Chipset specific sleep states
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+}
diff --git a/src/mainboard/prodrive/hermes/memory.c b/src/mainboard/prodrive/hermes/memory.c
new file mode 100644
index 0000000..d8822d3
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/memory.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/variants.h>
+#include <variant/gpio.h>
+#include <soc/cnl_memcfg_init.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg_cfg = {
+	/* Access memory info through SMBUS. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA0}
+	},
+	.spd[1] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA2}
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA4}
+	},
+	.spd[3] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xA6}
+	},
+
+	/* Baseboard uses 121, 81 and 100 rcomp resistors */
+	.rcomp_resistor = {121, 81, 100},
+
+	/*
+	 * Baseboard Rcomp target values.
+	 */
+	.rcomp_targets = {100, 40, 20, 20, 26},
+
+	/* Baseboard is an interleaved design */
+	.dq_pins_interleaved = 1,
+
+	/* Baseboard is using config 2 for vref_ca */
+	.vref_ca_config = 2,
+
+	/* Disable Early Command Training */
+	.ect = 0,
+};
+
+const struct cnl_mb_cfg *variant_memcfg_config(void)
+{
+	return &baseboard_memcfg_cfg;
+}
diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c
new file mode 100644
index 0000000..1074ea4
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/ramstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+
+	size_t num = 0;
+	const struct pad_config *gpio_table = get_gpio_table(&num);
+
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	gpio_configure_pads(gpio_table, num);
+
+	/* This must be one, otherwise FSP crashes ... */
+	params->PchHdaVcType = 0x1;
+}
diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c
new file mode 100644
index 0000000..8e8580a
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/romstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ * Copyright (C) 2017-2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+#include <variant/variants.h>
+#include <console/console.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config());
+}
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc b/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..d560afc
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc
@@ -0,0 +1,2 @@
+bootblock-y += gpio.c
+ramstage-y += gpio.c
\ No newline at end of file
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt b/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
new file mode 100644
index 0000000..80dba95
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt
@@ -0,0 +1,7 @@
+Category: server
+Vendor name: Prodrive
+Board name: Hermes
+Board URL: TBD
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c
new file mode 100644
index 0000000..1f09215
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c
@@ -0,0 +1,443 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "include/variant/gpio.h"
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPP_A ------- */
+	/* GPP_A0 - ESPI_ALERT1# */
+	PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A1 - ESPI_IO0 */
+	PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A2 - ESPI_IO1 */
+	PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A3 - ESPI_IO2 */
+	PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A4 - ESPI_IO3 */
+	PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A5 - ESPI_CS0# */
+	PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A6 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A6, NONE, DEEP, OFF),
+	/* GPP_A7 - ESPI_ALERT0# */
+	PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A8 - CLKRUN# */
+	PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF),
+	/* GPP_A9 - ESPI_CLK */
+	PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF3, TX_RX_DISABLE, OFF),
+	/* GPP_A10 - CLKOUT_LPC1 */
+	PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPP_A11 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A11, NONE, DEEP, OFF),
+	/* GPP_A12 - GPIO */
+	PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, YES),
+	/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
+	PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPP_A15 - SUSACK# */
+	PAD_CFG_NF_BUF_TRIG(GPP_A15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_A16 - GPIO */
+	PAD_CFG_GPO(GPP_A16, 0, DEEP),
+	/* GPP_A17 - GPIO */
+	PAD_CFG_GPO(GPP_A17, 0, DEEP),
+	/* GPP_A18 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A18, NONE, DEEP, OFF),
+	/* GPP_A19 - RESERVED */
+	/* GPP_A20 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A20, NONE, DEEP, OFF),
+	/* GPP_A21 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A21, NONE, DEEP, OFF),
+	/* GPP_A22 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A22, NONE, DEEP, OFF),
+	/* GPP_A23 - GPIO */
+	PAD_CFG_GPI_INT(GPP_A23, NONE, DEEP, OFF),
+
+	/* ------- GPIO Group GPP_B ------- */
+	/* GPP_B0 - GPIO */
+	PAD_CFG_GPO(GPP_B0, 0, DEEP),
+	/* GPP_B1 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B1, NONE, DEEP, OFF),
+	/* GPP_B2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B2, NONE, DEEP, OFF),
+	/* GPP_B3 - GPIO */
+	PAD_CFG_GPO(GPP_B3, 0, DEEP),
+	/* GPP_B4 - GPIO */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* GPP_B5 - GPIO */
+	PAD_CFG_GPO(GPP_B5, 0, DEEP),
+	/* GPP_B6 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B6, NONE, DEEP, OFF),
+	/* GPP_B7 - GPIO */
+	PAD_CFG_GPO(GPP_B7, 0, DEEP),
+	/* GPP_B8 - GPIO */
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	/* GPP_B9 - GPIO */
+	PAD_CFG_GPO(GPP_B9, 0, DEEP),
+	/* GPP_B10 - GPIO */
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	/* GPP_B11 - GPIO */
+	PAD_CFG_GPO(GPP_B11, 0, DEEP),
+	/* GPP_B14 - SPKR */
+	PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_B15 - GPIO */
+	PAD_CFG_GPO(GPP_B15, 1, DEEP),
+	/* GPP_B16 - GPIO */
+	PAD_CFG_GPO(GPP_B16, 1, DEEP),
+	/* GPP_B17 - GPIO */
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	/* GPP_B18 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B18, NONE, DEEP, OFF),
+	/* GPP_B19 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B19, NONE, DEEP, OFF),
+	/* GPP_B20 - GPIO */
+	PAD_CFG_GPO(GPP_B20, 1, DEEP),
+	/* GPP_B21 - GPIO */
+	PAD_CFG_GPO(GPP_B21, 1, DEEP),
+	/* GPP_B22 - GPIO */
+	PAD_CFG_GPI_INT(GPP_B22, NONE, DEEP, OFF),
+	/* GPP_B23 - PCHHOT# */
+	PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, DEEP, NF2, TX_RX_DISABLE, OFF),
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	/* GPP_C0 - RESERVED */
+	/* GPP_C1 - RESERVED */
+	/* GPP_C2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_C2, NONE, DEEP, OFF),
+	/* GPP_C3 - RESERVED */
+	/* GPP_C4 - RESERVED */
+	/* GPP_C8 - GPIO */
+	PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF),
+	/* GPP_C9 - GPIO */
+	PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF),
+	/* GPP_C10 - GPIO */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* GPP_C11 - GPIO */
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
+	/* GPP_C12 - GPIO */
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	/* GPP_C13 - GPIO */
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),
+	/* GPP_C14 - GPIO */
+	PAD_CFG_GPI_INT(GPP_C14, NONE, DEEP, OFF),
+	/* GPP_C15 - GPIO */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	/* GPP_C16 - I2C0_SDA */
+	PAD_CFG_NF_BUF_TRIG(GPP_C16, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPP_C17 - I2C0_SCL */
+	PAD_CFG_NF_BUF_TRIG(GPP_C17, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPP_C18 - I2C1_SDA */
+	PAD_CFG_NF_BUF_TRIG(GPP_C18, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPP_C19 - I2C1_SCL */
+	PAD_CFG_NF_BUF_TRIG(GPP_C19, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPP_C20 - RESERVED */
+	/* GPP_C21 - GPIO */
+	PAD_CFG_GPO(GPP_C21, 1, DEEP),
+	/* GPP_C22 - GPIO */
+	PAD_CFG_GPI_ACPI_SMI(GPP_C22, NONE, PLTRST, YES),
+	/* GPP_C23 - GPIO */
+	PAD_CFG_GPI_INT(GPP_C23, NONE, DEEP, OFF),
+
+	/* ------- GPIO Group GPP_D ------- */
+	/* GPP_D0 - GPIO */
+	PAD_CFG_GPI_NMI(GPP_D0, NONE, PLTRST, EDGE_SINGLE, YES),
+	/* GPP_D1 - GPIO */
+	PAD_CFG_GPO(GPP_D1, 1, PLTRST),
+	/* GPP_D2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF),
+	/* GPP_D3 - GPIO */
+	PAD_CFG_GPI_INT(GPP_D3, NONE, DEEP, OFF),
+	/* GPP_D4 - GPIO */
+	PAD_CFG_GPI_INT(GPP_D4, NONE, DEEP, OFF),
+	/* GPP_D5 - GPIO */
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),
+	/* GPP_D6 - GPIO */
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	/* GPP_D7 - GPIO */
+	PAD_CFG_GPO(GPP_D7, 0, DEEP),
+	/* GPP_D8 - GPIO */
+	PAD_CFG_GPO(GPP_D8, 0, DEEP),
+	/* GPP_D9 - GPIO */
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	/* GPP_D10 - GPIO */
+	PAD_CFG_GPO(GPP_D10, 0, DEEP),
+	/* GPP_D11 - GPIO */
+	PAD_CFG_GPO(GPP_D11, 0, DEEP),
+	/* GPP_D12 - GPIO */
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	/* GPP_D13 - GPIO */
+	PAD_CFG_GPO(GPP_D13, 0, DEEP),
+	/* GPP_D14 - GPIO */
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),
+	/* GPP_D15 - GPIO */
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	/* GPP_D16 - GPIO */
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),
+	/* GPP_D17 - GPIO */
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	/* GPP_D18 - GPIO */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	/* GPP_D19 - GPIO */
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+	/* GPP_D20 - GPIO */
+	PAD_CFG_GPO(GPP_D20, 0, DEEP),
+	/* GPP_D21 - GPIO */
+	PAD_CFG_GPO(GPP_D21, 0, DEEP),
+	/* GPP_D22 - GPIO */
+	PAD_CFG_GPO(GPP_D22, 0, DEEP),
+	/* GPP_D23 - GPIO */
+	PAD_CFG_GPO(GPP_D23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_G ------- */
+	/* GPP_G0 - GPIO */
+	PAD_CFG_GPO(GPP_G0, 0, DEEP),
+	/* GPP_G1 - GPIO */
+	PAD_CFG_GPO(GPP_G1, 0, DEEP),
+	/* GPP_G2 - GPIO */
+	PAD_CFG_GPO(GPP_G2, 0, DEEP),
+	/* GPP_G3 - GPIO */
+	PAD_CFG_GPO(GPP_G3, 0, DEEP),
+	/* GPP_G4 - GPIO */
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),
+	/* GPP_G5 - GPIO */
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),
+	/* GPP_G6 - GPIO */
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),
+	/* GPP_G7 - GPIO */
+	PAD_CFG_GPO(GPP_G7, 0, DEEP),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPD ------- */
+	/* GPD0 - GPIO */
+	PAD_CFG_GPO(GPD0, 0, DEEP),
+	/* GPD1 - ACPRESENT */
+	PAD_CFG_NF_BUF_TRIG(GPD1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD2 - LAN_WAKE# */
+	PAD_CFG_NF_BUF_TRIG(GPD2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD3 - PRWBTN# */
+	PAD_CFG_NF_BUF_TRIG(GPD3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD4 - SLP_S3# */
+	PAD_CFG_NF_BUF_TRIG(GPD4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD5 - SLP_S4# */
+	PAD_CFG_NF_BUF_TRIG(GPD5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD6 - SLP_A# */
+	PAD_CFG_NF_BUF_TRIG(GPD6, NONE, DEEP, NF1, RX_DISABLE, OFF),
+	/* GPD7 - GPIO */
+	PAD_CFG_GPI_INT(GPD7, NONE, DEEP, OFF),
+	/* GPD8 - SUSCLK */
+	PAD_CFG_NF_BUF_TRIG(GPD8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD9 - GPIO */
+	PAD_CFG_GPO(GPD9, 0, DEEP),
+	/* GPD10 - SLP_S5# */
+	PAD_CFG_NF_BUF_TRIG(GPD10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPD11 - GPIO */
+	PAD_CFG_GPO(GPD11, 0, DEEP),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_K ------- */
+	/* GPP_K0 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K0, NONE, DEEP, OFF),
+	/* GPP_K1 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K1, NONE, DEEP, OFF),
+	/* GPP_K2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K2, NONE, DEEP, OFF),
+	/* GPP_K3 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K3, NONE, DEEP, OFF),
+	/* GPP_K4 - GPIO */
+	PAD_CFG_GPO(GPP_K4, 0, DEEP),
+	/* GPP_K5 - GPIO */
+	PAD_CFG_GPO(GPP_K5, 0, DEEP),
+	/* GPP_K6 - GPIO */
+	PAD_CFG_GPO(GPP_K6, 0, DEEP),
+	/* GPP_K7 - GPIO */
+	PAD_CFG_GPO(GPP_K7, 0, DEEP),
+	/* GPP_K8 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K8, NONE, DEEP, OFF),
+	/* GPP_K9 - GPIO */
+	PAD_CFG_GPO(GPP_K9, 0, DEEP),
+	/* GPP_K10 - GPIO */
+	PAD_CFG_GPO(GPP_K10, 0, DEEP),
+	/* GPP_K11 - GPIO */
+	PAD_CFG_GPO(GPP_K11, 0, DEEP),
+	/* GPP_K12 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K12, NONE, DEEP, OFF),
+	/* GPP_K13 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K13, NONE, DEEP, OFF),
+	/* GPP_K14 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K14, NONE, DEEP, OFF),
+	/* GPP_K15 - GPIO */
+	PAD_CFG_GPO(GPP_K15, 0, DEEP),
+	/* GPP_K16 - GPIO */
+	PAD_CFG_GPO(GPP_K16, 0, DEEP),
+	/* GPP_K17 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K17, NONE, DEEP, OFF),
+	/* GPP_K18 - GPIO */
+	PAD_CFG_GPO(GPP_K18, 1, DEEP),
+	/* GPP_K19 - SMI# */
+	PAD_CFG_NF_BUF_TRIG(GPP_K19, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_K20 - GPIO */
+	PAD_CFG_GPO(GPP_K20, 0, DEEP),
+	/* GPP_K21 - GPIO */
+	PAD_CFG_GPO(GPP_K21, 0, DEEP),
+	/* GPP_K22 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K22, NONE, DEEP, OFF),
+	/* GPP_K23 - GPIO */
+	PAD_CFG_GPI_INT(GPP_K23, NONE, DEEP, OFF),
+
+	/* ------- GPIO Group GPP_H ------- */
+	/* GPP_H0 - GPIO */
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+	/* GPP_H1 - GPIO */
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	/* GPP_H2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_H2, NONE, DEEP, OFF),
+	/* GPP_H3 - GPIO */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
+	/* GPP_H4 - GPIO */
+	PAD_CFG_GPO(GPP_H4, 0, DEEP),
+	/* GPP_H5 - RESERVED */
+	/* GPP_H6 - GPIO */
+	PAD_CFG_GPO(GPP_H6, 0, DEEP),
+	/* GPP_H7 - GPIO */
+	PAD_CFG_GPO(GPP_H7, 0, DEEP),
+	/* GPP_H8 - GPIO */
+	PAD_CFG_GPO(GPP_H8, 0, DEEP),
+	/* GPP_H9 - GPIO */
+	PAD_CFG_GPO(GPP_H9, 0, DEEP),
+	/* GPP_H10 - RESERVED */
+	/* GPP_H11 - RESERVED */
+	/* GPP_H12 - GPIO */
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+	/* GPP_H13 - RESERVED */
+	/* GPP_H14 - RESERVED */
+	/* GPP_H15 - GPIO */
+	PAD_CFG_GPI_INT(GPP_H15, NONE, PLTRST, OFF),
+	/* GPP_H16 - RESERVED */
+	/* GPP_H17 - RESERVED */
+	/* GPP_H18 - GPIO */
+	PAD_CFG_GPI_INT(GPP_H18, NONE, DEEP, OFF),
+	/* GPP_H19 - GPIO */
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),
+	/* GPP_H20 - GPIO */
+	PAD_CFG_GPO(GPP_H20, 1, PLTRST),
+	/* GPP_H21 - GPIO */
+	PAD_CFG_GPO(GPP_H21, 0, PLTRST),
+	/* GPP_H22 - GPIO */
+	PAD_CFG_GPO(GPP_H22, 0, PLTRST),
+	/* GPP_H23 - GPIO */
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_E ------- */
+	/* GPP_E0 - GPIO */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	/* GPP_E2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_E2, NONE, DEEP, OFF),
+	/* GPP_E3 - GPIO */
+	PAD_CFG_GPI_INT(GPP_E3, NONE, DEEP, OFF),
+	/* GPP_E4 - GPIO */
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	/* GPP_E5 - GPIO */
+	PAD_CFG_GPI_INT(GPP_E5, NONE, DEEP, OFF),
+	/* GPP_E6 - GPIO */
+	PAD_CFG_GPI_NMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, YES),
+	/* GPP_E7 - GPIO */
+	PAD_CFG_GPO(GPP_E7, 0, DEEP),
+	/* GPP_E8 - SATALED# */
+	PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* ------- GPIO Group GPP_F ------- */
+	/* GPP_F0 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F0, NONE, DEEP, OFF),
+	/* GPP_F1 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F1, NONE, DEEP, OFF),
+	/* GPP_F2 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F2, NONE, DEEP, OFF),
+	/* GPP_F3 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F3, NONE, DEEP, OFF),
+	/* GPP_F4 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F4, NONE, DEEP, OFF),
+	/* GPP_F5 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F5, NONE, DEEP, OFF),
+	/* GPP_F6 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F6, NONE, DEEP, OFF),
+	/* GPP_F7 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F7, NONE, DEEP, OFF),
+	/* GPP_F8 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F8, NONE, DEEP, OFF),
+	/* GPP_F9 - GPIO */
+	PAD_CFG_GPI_INT(GPP_F9, NONE, DEEP, OFF),
+	/* GPP_F10 - SATA_SCLOCK */
+	PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_F11 - SATA_SLOAD */
+	PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_F12 - SATA_SDATAOUT1 */
+	PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_F13 - SATA_SDATAOUT0 */
+	PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_F14 - GPIO */
+	PAD_CFG_GPO(GPP_F14, 0, DEEP),
+	/* GPP_F17 - GPIO */
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	/* GPP_F18 - GPIO */
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	/* GPP_F19 - GPIO */
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),
+	/* GPP_F20 - GPIO */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	/* GPP_F21 - GPIO */
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	/* GPP_F22 - GPIO */
+	PAD_CFG_GPO(GPP_F22, 0, DEEP),
+	/* GPP_J2 - n/a */
+	PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_J3 - n/a */
+	PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF),
+	/* GPP_J4 - GPIO */
+	PAD_CFG_GPI_INT(GPP_J4, NONE, DEEP, OFF),
+	/* GPP_J5 - GPIO */
+	PAD_CFG_GPI_INT(GPP_J5, NONE, DEEP, OFF),
+	/* GPP_J6 - GPIO */
+	PAD_CFG_GPI_INT(GPP_J6, NONE, DEEP, OFF),
+	/* GPP_J7 - GPIO */
+	PAD_CFG_GPO(GPP_J7, 1, DEEP),
+	/* GPP_J8 - GPIO */
+	PAD_CFG_GPO(GPP_J8, 1, DEEP),
+	/* GPP_J9 - GPIO */
+	PAD_CFG_GPI_INT(GPP_J9, NONE, DEEP, OFF),
+	/* GPP_J10 - GPIO */
+	PAD_CFG_GPI_INT(GPP_J10, NONE, DEEP, OFF),
+	/* GPP_J11 - GPIO */
+	PAD_CFG_GPI_INT(GPP_J11, NONE, DEEP, OFF),
+};
+
+/* Early pad configuration in romstage. */
+const struct pad_config early_gpio_table[] = {
+	/* GPP_B0 - GPIO */
+	PAD_CFG_GPO(GPP_B0, 1, DEEP),
+};
+
+const struct pad_config *get_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *get_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h
new file mode 100644
index 0000000..f38f6c1
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h
@@ -0,0 +1,28 @@
+/*
+* This file is part of the coreboot project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; version 2 of
+* the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*/
+
+#ifndef PCH_GPIO_H
+#define PCH_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include <intelblocks/gpio_defs.h>
+
+const struct pad_config *get_gpio_table(size_t *num);
+const struct pad_config *get_early_gpio_table(size_t *num);
+
+
+
+
+#endif /* PCH_GPIO_H */
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h
new file mode 100644
index 0000000..83cf232
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h
@@ -0,0 +1,4 @@
+#include <soc/cnl_memcfg_init.h>
+
+/* Return memory configuration structure. */
+const struct cnl_mb_cfg *variant_memcfg_config(void);
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
new file mode 100644
index 0000000..4735d92
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -0,0 +1,121 @@
+chip soc/intel/cannonlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "1"
+	register "SataPortsEnable[4]" = "1"
+	register "SataPortsEnable[5]" = "1"
+	register "SataPortsEnable[6]" = "1"
+	register "SataPortsEnable[7]" = "1"
+
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpEnable[21]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "0x80"
+	register "PcieClkSrcUsage[1]" = "0x80"
+	register "PcieClkSrcUsage[2]" = "0x80"
+	register "PcieClkSrcUsage[3]" = "0x80"
+	register "PcieClkSrcUsage[4]" = "0x80"
+	register "PcieClkSrcUsage[5]" = "0x80"
+	register "PcieClkSrcUsage[6]" = "0x80"
+	register "PcieClkSrcUsage[7]" = "0x80"
+	register "PcieClkSrcUsage[8]" = "0x80"
+	register "PcieClkSrcUsage[9]" = "0x80"
+	register "PcieClkSrcUsage[10]" = "0x80"
+	register "PcieClkSrcUsage[11]" = "0x80"
+	register "PcieClkSrcUsage[12]" = "0x80"
+	register "PcieClkSrcUsage[13]" = "0x80"
+	register "PcieClkSrcUsage[14]" = "0x80"
+	register "PcieClkSrcUsage[15]" = "0x80"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	register "gen1_dec" = "0x000c0ca1"	# IPMI KCS
+
+	# USB Config 2.0/3.0
+
+	# USB OC0
+	register "usb2_ports[0]"		= "USB2_PORT_MID(OC0)"
+	register "usb2_ports[2]"		= "USB2_PORT_MID(OC0)"
+
+	# USB OC1
+	register "usb2_ports[1]"		= "USB2_PORT_MID(OC1)"
+	register "usb3_ports[3]"		= "USB3_PORT_DEFAULT(OC1)"
+
+	# USB OC2
+	register "usb2_ports[3]"		= "USB2_PORT_MID(OC2)"
+	register "usb2_ports[5]"		= "USB2_PORT_MID(OC2)"
+	register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC2)"
+	register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC2)"
+
+	# USB OC3
+	register "usb2_ports[4]"		= "USB2_PORT_MID(OC3)"
+	register "usb2_ports[6]"		= "USB2_PORT_MID(OC3)"
+
+	# USB OC4
+	register "usb2_ports[7]"		= "USB2_PORT_MID(OC4)"
+	register "usb2_ports[9]"		= "USB2_PORT_MID(OC4)"
+
+	# USB OC5
+	register "usb2_ports[8]"		= "USB2_PORT_MID(OC5)"
+	register "usb2_ports[10]"		= "USB2_PORT_MID(OC5)"
+	register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC5)"
+	register "usb3_ports[4]"		= "USB3_PORT_DEFAULT(OC5)"
+
+	# USB KCS
+	register "usb2_ports[13]"	= "USB2_PORT_MID(OC_SKIP)"
+
+	# USB OC6/7 - not connected
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# HECI
+	register "HeciEnabled" = "1"
+
+	# Internal GFX
+	register "InternalGfx" = "0"
+
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+
+	device domain 0 on
+		device pci 1b.0 on  end # PCIe Bridge
+		device pci 1b.4 on  end # onboard Ethernet
+		device pci 1b.5 on  end # onboard Ethernet
+		device pci 1c.0 on  end # PCIe Bridge
+		device pci 1c.1 on  end # Aspeed Graphics
+		device pci 1c.4 on  end # NVMe PCIE x4
+		device pci 1d.0 on  end # PCIE x4
+	end
+end
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Gerrit-Change-Number: 38303
Gerrit-PatchSet: 1
Gerrit-Owner: Christian Walter christian.walter@9elements.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: mainboard/prodrive/hermes: Add Support for Prodrive Hermes Board