Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43842 )
Change subject: soc/skylake: Configure SATA options only if SATA is enabled ......................................................................
soc/skylake: Configure SATA options only if SATA is enabled
Change-Id: I2860375c8ec4f9cda7709ee26db4c132a3b252b9 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chip.c 1 file changed, 23 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43842/1
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6ef01d8..52e4d30 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -166,14 +166,29 @@ } }
- memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, - sizeof(params->SataPortsHotPlug)); - memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, - sizeof(params->SataPortsSpinUp)); + params->SataEnable = config->EnableSata; + if (config->EnableSata) { + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); + + params->SataSalpSupport = config->SataSalpSupport; + params->SataMode = config->SataMode; + params->SataSpeedLimit = config->SataSpeedLimit; + /* + * For unknown reasons FSP skips writing some essential SATA init registers + * (SIR) when SataPwrOptEnable=0. This results in link errors, "unaligned + * write" errors and others. Enabling this option solves these problems. + */ + params->SataPwrOptEnable = 1; + tconfig->SataTestMode = config->SataTestMode; + } + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, @@ -233,7 +248,6 @@ params->PchLanClkReqSupported = config->LanClkReqSupported; params->PchLanClkReqNumber = config->LanClkReqNumber; } - params->SataSalpSupport = config->SataSalpSupport; params->SsicPortEnable = config->SsicPortEnable; params->ScsEmmcEnabled = config->ScsEmmcEnabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; @@ -257,22 +271,12 @@ params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable; - params->SataEnable = config->EnableSata; - params->SataMode = config->SataMode; - params->SataSpeedLimit = config->SataSpeedLimit; params->EnableTcoTimer = !config->PmTimerDisabled;
- /* - * For unknown reasons FSP skips writing some essential SATA init registers (SIR) when - * SataPwrOptEnable=0. This results in link errors, "unaligned write" errors and others. - * Enabling this option solves these problems. - */ - params->SataPwrOptEnable = 1;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; - tconfig->SataTestMode = config->SataTestMode; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43842 )
Change subject: soc/skylake: Configure SATA options only if SATA is enabled ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43842 )
Change subject: soc/skylake: Configure SATA options only if SATA is enabled ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43842 )
Change subject: soc/skylake: Configure SATA options only if SATA is enabled ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43842 )
Change subject: soc/skylake: Configure SATA options only if SATA is enabled ......................................................................
soc/skylake: Configure SATA options only if SATA is enabled
Change-Id: I2860375c8ec4f9cda7709ee26db4c132a3b252b9 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/43842 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Michael Niewöhner --- M src/soc/intel/skylake/chip.c 1 file changed, 23 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 6ef01d8..52e4d30 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -166,14 +166,29 @@ } }
- memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); - memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); - memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, - sizeof(params->SataPortsHotPlug)); - memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, - sizeof(params->SataPortsSpinUp)); + params->SataEnable = config->EnableSata; + if (config->EnableSata) { + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); + + params->SataSalpSupport = config->SataSalpSupport; + params->SataMode = config->SataMode; + params->SataSpeedLimit = config->SataSpeedLimit; + /* + * For unknown reasons FSP skips writing some essential SATA init registers + * (SIR) when SataPwrOptEnable=0. This results in link errors, "unaligned + * write" errors and others. Enabling this option solves these problems. + */ + params->SataPwrOptEnable = 1; + tconfig->SataTestMode = config->SataTestMode; + } + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, @@ -233,7 +248,6 @@ params->PchLanClkReqSupported = config->LanClkReqSupported; params->PchLanClkReqNumber = config->LanClkReqNumber; } - params->SataSalpSupport = config->SataSalpSupport; params->SsicPortEnable = config->SsicPortEnable; params->ScsEmmcEnabled = config->ScsEmmcEnabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; @@ -257,22 +271,12 @@ params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable; - params->SataEnable = config->EnableSata; - params->SataMode = config->SataMode; - params->SataSpeedLimit = config->SataSpeedLimit; params->EnableTcoTimer = !config->PmTimerDisabled;
- /* - * For unknown reasons FSP skips writing some essential SATA init registers (SIR) when - * SataPwrOptEnable=0. This results in link errors, "unaligned write" errors and others. - * Enabling this option solves these problems. - */ - params->SataPwrOptEnable = 1;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; - tconfig->SataTestMode = config->SataTestMode; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Michael Niewöhner (Code Review)
-
Patrick Rudolph (Code Review)