Change in coreboot[master]: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47533 )

Change subject: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
......................................................................

soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR

This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.

Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/nb_acpi.c
2 files changed, 6 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47533/1

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 3d3e803..5c7a667 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -49,6 +49,7 @@
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
    select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
    select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_P2SB
    select TSC_MONOTONIC_TIMER
    select UDELAY_TSC
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index 4a44980..f4d9da3 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -12,6 +12,7 @@
 #include <soc/pci_devs.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
+#include <intelblocks/p2sb.h>

#include "chip.h"

@@ -267,11 +268,12 @@
    	//BIT 15
    	if (num_hpets && (num_hpets != 0x1f) &&
    		(read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) {
+			union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf();
    		printk(BIOS_DEBUG, "    [Message-capable HPET Device] Enumeration ID: 0x%x, "
    			"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
-				0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM);
-			current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM,
-				HPET_DEV_NUM, HPET0_FUNC_NUM);
+				0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn);
+			current += acpi_create_dmar_ds_msi_hpet(current, 0, hpet_bdf.bus,
+				hpet_bdf.dev, hpet_bdf.fn);
    	}
    }

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47533 )

Change subject: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
......................................................................

Patch Set 2: Code-Review+2

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47533 )

Change subject: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
......................................................................

Patch Set 6: Code-Review+2

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47533 )

Change subject: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
......................................................................

soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR

This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.

Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533
Reviewed-by: Christian Walter 
Reviewed-by: Marc Jones 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/nb_acpi.c
2 files changed, 6 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marc Jones: Looks good to me, approved
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 3d3e803..5c7a667 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -49,6 +49,7 @@
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
    select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
    select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_P2SB
    select TSC_MONOTONIC_TIMER
    select UDELAY_TSC
    select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index 6d6eb00..29f533f 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -12,6 +12,7 @@
 #include <soc/pci_devs.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
+#include <intelblocks/p2sb.h>

#include "chip.h"

@@ -267,11 +268,12 @@
    	//BIT 15
    	if (num_hpets && (num_hpets != 0x1f) &&
    		(read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) {
+			union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf();
    		printk(BIOS_DEBUG, "    [Message-capable HPET Device] Enumeration ID: 0x%x, "
    			"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
-				0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM);
-			current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM,
-				HPET_DEV_NUM, HPET0_FUNC_NUM);
+				0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn);
+			current += acpi_create_dmar_ds_msi_hpet(current, 0, hpet_bdf.bus,
+				hpet_bdf.dev, hpet_bdf.fn);
    	}
    }