Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller

[Eric Lai (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath.
Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 )

Change subject: soc/intel/alderlake: Add support for UFS controller
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Patch Set 1:

(1 comment)

Patchset:

PS1: 
Copied my question here:
This is define in eltherlake
#define  PCH_DEV_UFS0		_PCH_DEV(SIO0, 5)
#define  PCH_DEV_UFS1		_PCH_DEV(SIO0, 7)
Icelake use 5 #define  PCH_DEVFN_UFS		_PCH_DEVFN(THERMAL, 5)
Alderlake use 7 #define  PCH_DEVFN_UFS		_PCH_DEVFN(ISH, 7)

If it's really port2, need Intel update the EDS and add some comment in the UPD. Per EDS, if only support 1 UFS should be index 0...