Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19490 )
Change subject: soc/intel/common: Add PCI configuration code for UART ......................................................................
soc/intel/common: Add PCI configuration code for UART
Add PCI configuration code support for intel/common/ block/uart module.
Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/19490 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Makefile.inc M src/soc/intel/common/block/uart/uart.c 3 files changed, 41 insertions(+), 2 deletions(-)
Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index ed4c7f0..b46edd7 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -17,8 +17,11 @@ #define SOC_INTEL_COMMON_BLOCK_UART_H
#include <arch/io.h> +#include <device/device.h>
void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, uint32_t clk_n_val);
+void pch_uart_read_resources(struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc index 13f5da8..0ec5314 100644 --- a/src/soc/intel/common/block/uart/Makefile.inc +++ b/src/soc/intel/common/block/uart/Makefile.inc @@ -1 +1,2 @@ -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c \ No newline at end of file +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c \ No newline at end of file diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 729a31b..8c5e454 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -12,8 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <device/device.h> +#include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ids.h> #include <intelblocks/lpss.h> #include <intelblocks/uart.h>
@@ -33,3 +35,36 @@ /* Set M and N divisor inputs and enable clock */ lpss_clk_update(baseaddr, clk_m_val, clk_n_val); } + +#if ENV_RAMSTAGE + +__attribute__((weak)) void pch_uart_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &pch_uart_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_UART0, + PCI_DEVICE_ID_INTEL_SPT_UART1, + PCI_DEVICE_ID_INTEL_SPT_UART2, + PCI_DEVICE_ID_INTEL_KBP_H_UART0, + PCI_DEVICE_ID_INTEL_KBP_H_UART1, + PCI_DEVICE_ID_INTEL_KBP_H_UART2, + PCI_DEVICE_ID_INTEL_APL_UART0, + PCI_DEVICE_ID_INTEL_APL_UART1, + PCI_DEVICE_ID_INTEL_APL_UART2, + PCI_DEVICE_ID_INTEL_APL_UART3, +}; + +static const struct pci_driver pch_uart __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif /* ENV_RAMSTAGE */