[S] Change in coreboot[master]: soc/intel/meteorlake: Implement SOC Die lock down configuration

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68430 )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/meteorlake: Implement SOC Die lock down configuration
......................................................................

soc/intel/meteorlake: Implement SOC Die lock down configuration

This patch implements a function to enable IOSF Primary Trunk Clock
Gating.

BUG=b:253210291
TEST=Able to build and boot rex to OS. Also needed for S0ix, tested
with Sandbox OS + Firmware combination for S0ix entry/exit.

Signed-off-by: Ravi Sarawadi 
Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430
Reviewed-by: Eric Lai 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/meteorlake/lockdown.c
1 file changed, 38 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Eric Lai: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c
index 678e63a..51fbdaf 100644
--- a/src/soc/intel/meteorlake/lockdown.c
+++ b/src/soc/intel/meteorlake/lockdown.c
@@ -2,10 +2,16 @@

#include <device/mmio.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
 #include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <stdint.h>

+/* PCR PSTH Control Register */
+#define PCR_PSTH_CTRLREG	0x1d00
+#define PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
+
 static void pmc_lock_pmsync(void)
 {
    uint8_t *pmcbase;
@@ -53,8 +59,19 @@
    	pmc_lock_smi();
 }

+static void soc_die_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
 void soc_lockdown_config(int chipset_lockdown)
 {
    /* PMC lock down configuration */
    pmc_lockdown_cfg(chipset_lockdown);
+	/* SOC Die lock down configuration */
+	soc_die_lockdown_cfg();
 }