[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Krishna P Bhat D, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 90:

(7 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83798/comment/56aff37a_530ab5ce?usp... :
PS50, Line 69: SOC_INTEL_COMMON_BLOCK_ME_SPEC_18
> > @[e-mail] Please update the 21.0 ME spec. […]

Sure, added to TODO bug.

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83798/comment/a9f5aaba_4385cc99?usp... :
PS71, Line 367: config FSP_PUBLISH_MBP_HOB
> note, those CLs are not merged yet, hence, you need to rebase your code later as well.

Sure.

File src/soc/intel/pantherlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/e183a2c0_fe679751?usp... :
PS37, Line 30: 	C_STATE_C0,		/* 0 */
             : 	C_STATE_C1,		/* 1 */
             : 	C_STATE_C1E,		/* 2 */
             : 	C_STATE_C6_SHORT_LAT,	/* 3 */
             : 	C_STATE_C6_LONG_LAT,	/* 4 */
             : 	C_STATE_C7_SHORT_LAT,	/* 5 */
             : 	C_STATE_C7_LONG_LAT,	/* 6 */
             : 	C_STATE_C7S_SHORT_LAT,	/* 7 */
             : 	C_STATE_C7S_LONG_LAT,	/* 8 */
             : 	C_STATE_C8,		/* 9 */
             : 	C_STATE_C9,		/* 10 */
             : 	C_STATE_C10,		/* 11 */
             : 	NUM_C_STATES
> > Hi, I will be back on this info. Checking internally with the owners. […]

Sure, added to TODO bug.

File src/soc/intel/pantherlake/chipset.cb:

https://review.coreboot.org/c/coreboot/+/83798/comment/3e5ef259_e28273c4?usp... :
PS50, Line 15:
> Hi,can we take up this to a crosbug, and mark TODO.

Sure, added to TODO bug.

File src/soc/intel/pantherlake/include/soc/cpu.h:

https://review.coreboot.org/c/coreboot/+/83798/comment/275cd37a_0876780e?usp... :
PS71, Line 7: #define C1_LATENCY	1
            : #define C6_LATENCY	127
            : #define C7_LATENCY	253
            : #define C8_LATENCY	260
            : #define C9_LATENCY	487
            : #define C10_LATENCY	1048
> same

Sure, added to TODO bug.

https://review.coreboot.org/c/coreboot/+/83798/comment/4e36f095_5d41afe7?usp... :
PS71, Line 15: #define C1_POWER	0x3e8
             : #define C6_POWER	0x15e
             : #define C7_POWER	0xc8
             : #define C8_POWER	0xc8
             : #define C9_POWER	0xc8
             : #define C10_POWER	0xc8
> > please confirm the applicability and authenticity of these values  for PTL SoC. […]

Sure, added to TODO bug.

File src/soc/intel/pantherlake/tcss.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/e8b2d0e2_1bd3b12f?usp... :
PS48, Line 6: const struct soc_tcss_ops tcss_ops = {
> > Hi Subrata,we will be requiring this, since TCSS I/O Manager is above 4GB. […]

Added to discuss more in TODO bug. Currently using skeleton code.