Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in the native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921 [2] Intel document #336067-007US
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43454/1
diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index 1c26564..97ab7cb 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -12,23 +12,23 @@ /* GPP_A0 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - PIRQA# */ - PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* GPP_A10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ @@ -59,9 +59,9 @@
/* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* GPP_B2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ @@ -83,11 +83,11 @@ /* GPP_B11 - GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPP_B12 - GLB_RST_WARN_N# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ @@ -105,7 +105,7 @@ /* GPP_B22 - GPIO */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2),
/* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ @@ -129,15 +129,15 @@ /* GPP_F9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* GPP_F12 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), /* GPP_F15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ @@ -147,22 +147,22 @@ /* GPP_F18 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* GPP_F21 - LAN_SMBALRT# */ - PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF3),
/* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ @@ -233,7 +233,7 @@ /* GPP_D14 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF3), /* GPP_D16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ @@ -259,7 +259,7 @@ /* GPP_E2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* GPP_E4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ @@ -269,9 +269,9 @@ /* GPP_E7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ @@ -287,11 +287,11 @@ /* GPD2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ @@ -303,18 +303,18 @@ /* GPD10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),
/* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF2), /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF2), /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF2), /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, DEEP, NF2), /* GPP_I4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ @@ -322,7 +322,7 @@ /* GPP_I6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF2), /* GPP_I8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ @@ -333,51 +333,51 @@ /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), /* GPP_J1 - LAN_LED_P0_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), /* GPP_J2 - LAN_LED_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* GPP_J3 - LAN_LED_P1_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* GPP_J4 - LAN_LED_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* GPP_J5 - LAN_LED_P2_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), /* GPP_J6 - LAN_LED_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), /* GPP_J7 - LAN_LED_P3_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J12, NONE, DEEP, NF1), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J13, NONE, DEEP, NF1), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J15, NONE, DEEP, NF1), /* GPP_J16 - LAN_SDP_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J16, NONE, DEEP, NF1), /* GPP_J17 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J18, NONE, DEEP, NF1), /* GPP_J19 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J20, NONE, DEEP, NF1), /* GPP_J21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J22, NONE, DEEP, NF1), /* GPP_J23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER),
@@ -397,13 +397,13 @@ /* GPP_K6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), /* GPP_K10 - PE_RST# */ - PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1),
/* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ @@ -442,11 +442,11 @@ /* GPP_G16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* GPP_G18 - NMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), @@ -501,7 +501,7 @@ /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* GPP_L2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 1:
Bryant, please test this patch on TiogaPass.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 1: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG@11 PS1, Line 11: the drop "the"
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG@13 PS1, Line 13: this fields these fields
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG@15 PS1, Line 15: 549921 Skylake Platform Controller Hub (PCH), H and LP BIOS Specification
(probably renamed if support for moar PCHs was added)
Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43454
to look at the new patch set (#2).
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Skylake/Kaby Lake H/LP Platform Controller Hub, December 2019, Intel document #549921 [2] Intel C620 Series Chipset Platform Controller Hub, Datasheet, May 2019, Intel document #336067-007US
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43454/2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 2:
(2 comments)
Thanks for the review
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG@11 PS1, Line 11: the
drop "the"
Done
https://review.coreboot.org/c/coreboot/+/43454/1//COMMIT_MSG@13 PS1, Line 13: this fields
these fields
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43454/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43454/2//COMMIT_MSG@15 PS2, Line 15: , BIOS Specification?
Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43454
to look at the new patch set (#3).
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Skylake/Kaby Lake H/LP Platform Controller Hub, BIOS Specification, December 2019, Intel document #549921 [2] Intel C620 Series Chipset Platform Controller Hub, Datasheet, May 2019, Intel document #336067-007US
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43454/3
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43454/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43454/2//COMMIT_MSG@15 PS2, Line 15: ,
BIOS Specification?
Yes )
Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43454
to look at the new patch set (#4).
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921 [2] Intel document #336067-007US
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43454/4
Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43454
to look at the new patch set (#5).
Change subject: 2/4 mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
2/4 mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921 [2] Intel document #336067-007US
This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - 1/4 cedarisland: undo set trig and bufdis for NF pads CB:43454 - 2/4 tiogapass: undo set trig and bufdis for NF pads CB:43561 - 3/4 h110m: undo set trig and bufdis for NF pads CB:43569 - 4/4 soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43454/5
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: 2/4 mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 5: Code-Review+2
Hello Lance Zhao, build bot (Jenkins), Jonathan Zhang, Angel Pons, Bryant Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43454
to look at the new patch set (#6).
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921 [2] Intel document #336067-007US
This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43454/6
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
Patch Set 6: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43454 )
Change subject: mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads ......................................................................
mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921 [2] Intel document #336067-007US
This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h 1 file changed, 66 insertions(+), 66 deletions(-)
Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index 1c26564..97ab7cb 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -12,23 +12,23 @@ /* GPP_A0 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), /* GPP_A1 - LAD0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* GPP_A5 - LFRAME# */ - PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* GPP_A6 - SERIRQ */ - PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - PIRQA# */ - PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* GPP_A10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), /* GPP_A11 - GPIO */ @@ -59,9 +59,9 @@
/* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF_BUF_TRIG(GPP_B0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF_BUF_TRIG(GPP_B1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* GPP_B2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), /* GPP_B3 - GPIO */ @@ -83,11 +83,11 @@ /* GPP_B11 - GPIO */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPP_B12 - GLB_RST_WARN_N# */ - PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), /* GPP_B16 - GPIO */ @@ -105,7 +105,7 @@ /* GPP_B22 - GPIO */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, RSMRST, NF2, RX_DISABLE, LEVEL), + PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2),
/* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ @@ -129,15 +129,15 @@ /* GPP_F9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* GPP_F12 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_F14, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), /* GPP_F15 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), /* GPP_F16 - GPIO */ @@ -147,22 +147,22 @@ /* GPP_F18 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF_BUF_TRIG(GPP_F19, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF_BUF_TRIG(GPP_F20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* GPP_F21 - LAN_SMBALRT# */ - PAD_CFG_NF_BUF_TRIG(GPP_F21, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF_BUF_TRIG(GPP_F22, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF_BUF_TRIG(GPP_F23, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF3),
/* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - RESERVED */ /* GPP_C1 - RESERVED */ /* GPP_C2 - SMBALERT# */ - PAD_CFG_NF_BUF_TRIG(GPP_C2, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ /* GPP_C5 - GPIO */ @@ -233,7 +233,7 @@ /* GPP_D14 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF_BUF_TRIG(GPP_D15, NONE, DEEP, NF3, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF3), /* GPP_D16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), /* GPP_D17 - GPIO */ @@ -259,7 +259,7 @@ /* GPP_E2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* GPP_E4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), /* GPP_E5 - GPIO */ @@ -269,9 +269,9 @@ /* GPP_E7 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* GPP_E10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), /* GPP_E11 - GPIO */ @@ -287,11 +287,11 @@ /* GPD2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), /* GPD3 - PWRBTN# */ - PAD_CFG_NF_BUF_TRIG(GPD3, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* GPD4 - SLP_S3# */ - PAD_CFG_NF_BUF_TRIG(GPD4, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - PAD_CFG_NF_BUF_TRIG(GPD5, NONE, RSMRST, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ @@ -303,18 +303,18 @@ /* GPD10 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), /* GPD11 - GBEPHY */ - PAD_CFG_NF_BUF_TRIG(GPD11, NONE, RSMRST, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),
/* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_I ------- */ /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF2), /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF2), /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF2), /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, DEEP, NF2, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_I3, NONE, DEEP, NF2), /* GPP_I4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), /* GPP_I5 - GPIO */ @@ -322,7 +322,7 @@ /* GPP_I6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF2, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF2), /* GPP_I8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), /* GPP_I9 - GPIO */ @@ -333,51 +333,51 @@ /* ------- GPIO Community 4 ------- */ /* ------- GPIO Group GPP_J ------- */ /* GPP_J0 - LAN_LED_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J0, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), /* GPP_J1 - LAN_LED_P0_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J1, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), /* GPP_J2 - LAN_LED_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J2, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* GPP_J3 - LAN_LED_P1_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J3, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* GPP_J4 - LAN_LED_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J4, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* GPP_J5 - LAN_LED_P2_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J5, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), /* GPP_J6 - LAN_LED_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J6, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), /* GPP_J7 - LAN_LED_P3_1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J8, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J9, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J10, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - PAD_CFG_NF_BUF_TRIG(GPP_J11, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J12, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J12, NONE, DEEP, NF1), /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - PAD_CFG_NF_BUF_TRIG(GPP_J13, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J13, NONE, DEEP, NF1), /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J14, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - PAD_CFG_NF_BUF_TRIG(GPP_J15, NONE, DEEP, NF1, NO_DISABLE, OFF), + PAD_CFG_NF(GPP_J15, NONE, DEEP, NF1), /* GPP_J16 - LAN_SDP_P0_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J16, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J16, NONE, DEEP, NF1), /* GPP_J17 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), /* GPP_J18 - LAN_SDP_P1_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J18, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J18, NONE, DEEP, NF1), /* GPP_J19 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), /* GPP_J20 - LAN_SDP_P2_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J20, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J20, NONE, DEEP, NF1), /* GPP_J21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), /* GPP_J22 - LAN_SDP_P3_0 */ - PAD_CFG_NF_BUF_TRIG(GPP_J22, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_J22, NONE, DEEP, NF1), /* GPP_J23 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER),
@@ -397,13 +397,13 @@ /* GPP_K6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), /* GPP_K7 - RESERVED */ - PAD_CFG_NF_BUF_TRIG(GPP_K7, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF_BUF_TRIG(GPP_K8, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_K9, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), /* GPP_K10 - PE_RST# */ - PAD_CFG_NF_BUF_TRIG(GPP_K10, NONE, DEEP, NF1, TX_DISABLE, OFF), + PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1),
/* ------- GPIO Community 5 ------- */ /* ------- GPIO Group GPP_G ------- */ @@ -442,11 +442,11 @@ /* GPP_G16 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* GPP_G18 - NMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* GPP_G19 - SMI# */ - PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, RX_DISABLE, OFF), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* GPP_G20 - RESERVED */ /* GPP_G21 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), @@ -501,7 +501,7 @@ /* ------- GPIO Group GPP_L ------- */ /* GPP_L0 - RESERVED */ /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF_BUF_TRIG(GPP_L1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), + PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), /* GPP_L2 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), /* GPP_L3 - GPIO */
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Patrick Georgi (Code Review)