[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 25:

(7 comments)

Patchset:

PS25:
> can you please add SoC override as well?

will add separate CL for override functions for PTL soc.

Commit Message:

https://review.coreboot.org/c/coreboot/+/84104/comment/7a652037_4ef95ba6?usp... :
PS11, Line 15: and check if GPE1 sts bits have been printed during boot.
> Paste the new debug messages?

Done

File src/soc/intel/common/block/include/intelblocks/pmclib.h:

https://review.coreboot.org/c/coreboot/+/84104/comment/0b1b7226_370f596f?usp... :
PS24, Line 254: return
> ```/* nop */```

Done

https://review.coreboot.org/c/coreboot/+/84104/comment/5254a62d_bfa04902?usp... :
PS24, Line 259: return
> ```/* nop */```

Done

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/e972bab0_57a1d1b7?usp... :
PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */
             : __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a)
             : {
             : 	return NULL;
             : }
             : 
             : /* disable the corresponding GPE1 bits based on standard GPE0 bits */
             : __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask)
             : {
             : }
             : 
             : /* enable the corresponding GPE1 bits based on standard GPE0 bits */
             : __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask)
             : {
             : }
> oh, that SOC_INTEL_COMMON_BLOCK_ should have been SOC_INTEL_COMMON_BLOCK_PMC; not sure where those f […]

Felix, build issue fixed?

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/33aad979_164e9356?usp... :
PS24, Line 421: 	print_std_gpe1_sts(gpe1_sts);
> shouldn't we print first and then reset ?

Similar to GPE0 in line 415, the STS values are read and saved prior to the reset. print function merely print the previous stored STS values.

https://review.coreboot.org/c/coreboot/+/84104/comment/1342bb6c_17dcb04b?usp... :
PS24, Line 522:
> one tab less?

Done