Change in coreboot[master]: soc/amd/cezanne/acpi: Add support for RTC workaround

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60172 )

Change subject: soc/amd/cezanne/acpi: Add support for RTC workaround
......................................................................

soc/amd/cezanne/acpi: Add support for RTC workaround

The RTC on Cezanne is an unstable wake source when the system is in
S0i3. We instead need to use an internal timer that triggers a GPIO that
acts as a wake source. This change provides the ACPI necessary to allow
the OS to manage the wake source.

BUG=b:209705576
TEST=Boot guybrush with this patch and several OS patches. Verified the
OS sets the correct wake bit, the system correctly suspends
and resumes, and the wake source is correctly accounted for.

Signed-off-by: Raul E Rangel 
Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e
---
A src/soc/amd/cezanne/acpi/rtc_workaround.asl
M src/soc/amd/cezanne/acpi/soc.asl
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/60172/1

diff --git a/src/soc/amd/cezanne/acpi/rtc_workaround.asl b/src/soc/amd/cezanne/acpi/rtc_workaround.asl
new file mode 100644
index 0000000..e69e974
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi/rtc_workaround.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Workaround for RTC on Cezanne.
+ * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thir...
+ */
+
+Scope (_SB.PEP) {
+	Name (_PRW, Package () {
+		Package() {_SB.GPIO, 0},
+		0x03
+	})
+}
+
+Scope (_SB.GPIO) {
+	Name (_AEI, ResourceTemplate () {
+		GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\_SB.GPIO",,,,)
+		{
+			44 /* int_shdwsysalarmfire */
+		}
+	})
+
+	Method (_E2C, 0, Serialized) {
+		Notify (_SB_.PEP, 0x02)
+	}
+}
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index e603307..bf2838a 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -27,6 +27,8 @@

#include <soc/amd/common/acpi/upep.asl>

+#include "rtc_workaround.asl"
+
 /*
  * Platform Wake Notify
  *